Re: gEDA-user: OT: (Vhdl help)

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Thu, 2008-06-26 at 20:06 -0400, Mike Jarabek wrote:
> >The code was designed for a CPLD, so perhaps there is a difference. In
> >ISE, with the FPGA I'm putting down buffer symbols which tell it what
> >kind of IO to use. If you could directly map the "INOUT" port to a pin
> >on the chip (where "0" or "Z" output states would make sense), that
> >works intuitively.
> 
> >What I couldn't do was take the inout lines, and connect them to the
> >outside world via an IOBUF.
> 
> Ahhh... This is where things went wrong. ISE is capable of inferring
> the IOBUF from the VHDL. The IOBUF is a primitive, that you can't
> connect to your 'internal' tri state bus. Best to connect the ports
> from the underlying module directly to 'inout' ports at the top level.

Super, thanks!

I got the Xilinx I2C core (with my mods) to synthesise, but I'll try
backing those changes out and tying the module directly to the output
pin's signal. I think I may have attempted that already - seem to recall
it synthesised, but gave a warning. Will look tomorrow.

[...]

> One thing to watch out for with your I2C interface is that you really
> should sample the SDA line half way through the bit period, and that
> you should filter the inputs, as they have really slow rise times.
> Every I2C block I have seen from vendors have clocked internal logic
> directly from the SCL line, and this is dangerous. Sample and re-time
> the line with a high rate clock and sample the SDA line at the right
> time, with a delay generated by the master clock.  In the past I have
> used a state machine to carry this out. 

The Xilinx application example carried a warning in the code to this
effect. Once I've got it resembling attempting to communicate I'll have
a look at putting in a better sampling section.

Thanks, and best regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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