Re: gEDA-user: Gnetlist -g PCB

[John Doty <jpd@xxxxxxxxxxxxx>]

On Jun 29, 2008, at 10:17 PM, Larry Doolittle wrote:

> On Mon, Jun 30, 2008 at 12:00:48AM -0400, al davis wrote:
>> On Sunday 29 June 2008, John Doty wrote:
>>>
>>>> It looks to me that geda has mixed the concepts of
>>>> discipline and direction.
>>>
>>> Yes, but the real problem is the mixing of such clerical
>>> concepts into what is really a set of applied physics issues.
>>
>> Interesting point .. There is nothing keeping you from
>> describing things like a one femtoHertz oscillator or a new CPU
>> with a 100 TeraHertz clock.  Building it, on the other hand,
>> might be a little difficult.
>
> I agree with both of you.  Let me add a little spin:
> Most designs don't challenge conventional rules to enter
> applied physics territory.

Well, many engineers *believe* this, but that's why they get burned.  
It seems to me that I am encountering problems of this sort more  
frequently (I'm often the troubleshooter). Consider the increasing  
use of FPGA and CPLD in low speed circuits. The trouble is that if  
you're using a part *capable* of 100 MHz operation, its connections  
need to be designed with that in mind. A 100 MHz wiring harness is  
tricky. One recent space mission got into trouble by choosing a fast  
microprocessor, "derating" its speed for "reliability", and using big  
klunky bypass caps, again for "reliability". Trouble was, the klunky  
caps had too much inductance for the actual processor speed.

All of the superstitions about "noise on ground" (huh?) and "ground  
loops" reflect attempts to enter applied physics territory without  
thinking physically.

The problem that set off this discussion was classifying the pins on  
a pot. A pot connected as a two port network may very well be thought  
of as a device with an "input" and an "output". But note that "input"  
and "output" really refer to ports, not pins. That's another reason  
why classifying pins is tricky: with a common "ground" you can often  
ignore the distinction. But not always, and that gets us back to the  
"noise on ground" illusion.

I think it very difficult to implement useful DRC-based on pin  
classification even for experts. For newbies, it's pure confusion. In  
the days of 4000 series CMOS, perhaps it was possible for pure  
digital circuits.

>   Some people are not qualified
> to design, analyze, and debug such circuits.  Other people
> are, but they have better things to do.  Even when they
> break new ground on part of the circuit, they still want
> their conventional control and monitoring junk around the
> outside to work right the first time, without some silly
> "d'oh" moment.
>
> As long as DRC covers the 90% usage case properly, and has
> a clean way to be told "don't look at this part of the circuit,
> I don't have time or interest to shoehorn my understanding
> of the applied physics into DRC nomenclature", DRC can be
> useful for everyone.

You are welcome to try to design such a thing. It seems to me that  
few understand where that line should be drawn, so the ability to  
draw it doesn't help.

>
>   - Larry
>   "If we knew what we were doing, it wouldn't be called research!"
>
>
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John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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