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Re: gEDA-user: PC emulator and HDL
Ahmad Sayed wrote:
>>> For example, for a PCI device, the HDL writer will need the test
>>> environment to create PCI cycles (including the clocks) at a *far*
>>> lower level then qemu, for example, provides. Emulating at the BUS
>>> cycle level would drastically slow down a PC emulator.
> PCI device simulation i think about but with some respect, but i did not
> have a well understanding to it yet, i have some theoretical background
> about it, i think Larry will help us, how he handles this in his project,
> but sorry if my question seems to be a bit silly and not practical , could I
> do the simulation at byte level or even at bit level. some thing like
> sending values to the PCI device and wait for response as bytes or bits?
[jg]Yes. iverilog can give you that data. You will have to take it from
a program that keeps iverilog fed with new tasks to return values for, and
then put those data values into the parallel port (a driver for parallel port in other words).
>
>>> For USB devices or firewire devices, you might be able make up a
>>> hookup point where you can tunnel from the emulator over to a
>>> simulation process.
> Good news at last :), as i mentioned earlier i already have a prototype with
> qemu and jHDL, I use named pipes to tunnels the data by modifying the
> parallel.c code in the qemu, but i could use better approach if i start it
> for real.
[jg]That may a good way to do it. Sounds reasonable to me...
I think maybe I understand your goal, but did not get a clear answer yet --
You want to run a HDL simulator on a qemu
virtual machine to drive simulated parallel port data going out and in so as to
interact with your custom hardware attached to physical parallel port.
Where I say "drive" means "code to connect data coming out of the HDL simulator
to the parallel.c code in the qemu", and also coming in.
Is that right?
--
Ecosensory Austin TX
tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1
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