Re: gEDA-user: PC emulator and HDL

[John Griessen <john@xxxxxxxxxxxxxx>]

Ahmad Sayed wrote:

> At the emulator side, which has a Linux preinstalled i wrote the C code,
> this code use unmodified outp and inp function to send/recieve data to the
> parallel port the parallel.c redirect the data to the named pipe which is
> read by the Parallel.java code and stimulate the full adder jHDL circuit,
> the JHDL full adder calcluate the the sum of the data and control register
> and put the data on the status port of the parallel port, the C code read
> the status port which contains the result.

[jg] OK, I get this.  It lets you use a PC as a simulation of hardware with up to 8 wires
with data speeds up to 2.7 MHz in some cases, 1 MHz for most any parallel port.

> 
> From user point of view
> All this details should be seamless, all he needs to do is to connect his
> circuit to Parallel port component in his HDL simulator testbench and write
> an ordinary device driver or user space code for his OS on the emulator.

Here I think you are talking of also having testbench HDL code along with the simulation
of your hardware being designed.  Sounds like a good thing for promoting
open HDL tools like jHDL and iverilog since you use a PC for most everything.

Are you thinking of making your special parallel port driver
GPL and eventually part of linux?  That would make a great tutorial approach for iverilog...

John Griessen


-- 
Ecosensory   Austin TX
tinyOS devel on:  ubuntu Linux;   tinyOS v2.0.2;   telosb ecosens1


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