Re: gEDA-user: random project idea

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

Steve -

On Fri, Mar 28, 2008 at 10:10:27AM -0700, Steve Meier wrote:
> High speed memory is now staggering the transmission of each data line
> to minimize cross talk. High end fpga's can support qdr II memory
> devices to clock speeds of over 500 MHz. The qdr ii has two data buses
> one for read and one for writing. Each bus supports a transfer on each
> edge of the clock. This implies data rates on these buses of over 1 GHz.
> 
> It isn't the bus rate that will limit performance it is the internal
> clock rate. 500 MHz as opposed to over 3 GHZ.

That still seems very fast compared to the 125-ish MHz I can reach 
synthesizing for Spartan-3.  OTOH, if I really cared, I would choose
a faster and more expensive chip family.

> However, the fpga has all those built in multipliers.... hundreds of
> them. So for certain tasks an fpga will completely blow away a standard
> intel based computer.

Yup.  Even at 125 MHz.

> My inclination would be to build a mother board with both a standard
> microprocessor and an additional fpga that can be programed by the
> microprocessor. A customized coprocessor so to speak.

OK.  Just be sure to give the FPGA direct access (via PHY) to
Ethernet.  The same concept also applies to network performance.
I'd venture to say you want four RJ-45's: two for the traditional
microprocessor and two for the FPGA.

  - Larry


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user