[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: GSchem in CMOS Analog IC context?


On Mar 8, 2009, at 1:12 PM, daledouglas@xxxxxxxxxxxxxx wrote:


John,
You've hit the nail on the head: I'm trying to usurp a Cadence flow for a high frequency continuous time analog design. As such, I have a lot of problems to overcome, but a rough order looks something like: 

1) download/build GSchem
2) find/build symbol library for TSMC XXX
The stock symbols shipped with gEDA are fine for this purpose, I think. For PCB layout I customize them, but for ASIC I mostly just attach attributes to library symbol instances. 

Have a look at this circuit:

Attachment: Comparator.sch
Description: Binary data
The only custom symbol (embedded) is the company printframe: all of the others are gEDA library symbols. So your library is already there, I think.
3) find a way to convert netlist to Spice format compatible w/TSMC parameterization (W,L,f,m,Corners) 

For the sample, the command is:

gnetlist -g spice-sdb --nomunge -o Comparator.cir Comparator.sch
You seem to be using parameters in a more elaborate way than I, so you may run into limits that I don't know about. Consult with Stuart here: he's very good about quickly fixing spice-sdb (thanks again for that critical one a couple of years ago, Stuart!).
4) find a way to do Monte Carlo, even if only with deltaVTH numbers from Pelgrom or Kinget 

Another one of Stuart's interests.


.
.
This is where, in my flow, the information disappears into a different contractor's hands. 


.
99) find/build robust open source LVS flow
For me, it reemerges as a parameter extracted netlist whose behavior I attempt to verify with SPICE (at ~1 day/us).
Yesterday I did #1. Today I'm working on #2. I would love to get a copy of the OpenIP library, thank you.

Attachment: openIP-alpha-20090308.tar.gz
Description: GNU Zip compressed data



Not complete or tested. Please review.
Are you saying that #3 is going to be harder than just downloading/ building GNetlist?
Not sure. What you want seems a bit more ambitious than I have tried so far. Still, I have working silicon, now baselined to fly on ASTRO- H in 2013 (http://astro-h.isas.jaxa.jp/). 



Many thanks,
Dale Douglas
http://www.linkedin.com/pub/2/184/925

-----Original Message-----

From: John Doty <jpd@xxxxxxxxx>
Sent: Mar 8, 2009 12:05 PM
To: gEDA user mailing list <geda-user@xxxxxxxxxxxxxx>
Cc: daledouglas@xxxxxxxxxxxxxx
Subject: Re: gEDA-user: GSchem in CMOS Analog IC context?


On Mar 8, 2009, at 7:22 AM, Stuart Brorson wrote:


Hi --
Has anyone successfully used GSchem in an CMOS analog IC context? -- 
I'm looking at a plain-vanilla +MIM TSMC CMOS process at the ~ 0.18
to 0.35u node. Has anyone built symbols for the typical TSMC nodes
(parameterized NMOS,CMOS,resistors with appropriate sheet resistance 
and tempco)?



Dale, assuming you're using SPICE, the question is whether the
currently maintained gnetlist back end (spice-sdb) understands the
parameter names. A regular resistor symbol should work fine with the
right attributes.

So, Stuart, does spice-sdb know how to transfer attributes to
parameters in the following syntax (ngspice)?

General form:

       RXXXXXXX n+ n- <value> <mname> <l=length> <w=width> <temp=val>
+ <dtemp=val> m=<val> <ac=val> <scale=val> <noisy = 0|1>
Peter Kaiser in Germany has done some chip designs using gEDA. Here's 
the website he put up recording some of his tips, including some
symbols for instantiating devices:

http://www.easyasic.com/

You might try contacting him in person if you have questions.  His
e-mail addr is on his website.

John Doty has also done mixed-signal designs using gEDA.  He has
published papers on his work, and has written an interesting gnetlist back-end, all of which he has posted on his website. I didn't see any 
schematic symbols on his website, but here's a link:

http://www.noqsi.com/home.html
John is very active on the e-mail list, so I expect that he'll turn up 
to provide more info to you soon.


Gotta be less predictable ;-)

Dale, I've done several design variations on my delta-sigma CCD
chains using 350 nm TSMC. However, I haven't gotten into careful
modeling of the resistors. I use very few resistors in these designs,
always in noncritical places. Gains are set by capacitor ratios.

If you're interested, I've been working on symbols for professor
Ikeda's OpenIP (http://research.kek.jp/people/ikeda/openIP/). I can
send you an alpha version of that library if you wish (you get to
check them, as I've only used a subset), and I can answer specific
questions if you can't read the Japanese documentation.

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx






_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user



John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user