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Re: gEDA-user: pcb drc checks before releasing pcb || cost diff. from vendor to vendor
S. Aguinaga wrote:
> Hello Fellow designers:
> I'm new to geda, I've designed my first board with gschem and pcb.
> First, do one of you have a check list of "must do" before releasing a
> board to a board
> fab house? I've used the DRC checks and I don't know if all are
> accurate or if all are needed.
> I've search the "seul.org" mail archives and there is a lot of info
> and didn't find
> a mention or such a list. If any of you have any advice regarding
> things I should
> check before I release the board to the fab house, please let me
> know.
you'll get a lot of different answers i'm sure. Here are some of the
things I check for. Note that this is not specific to geda/pcb.
review the photo plot files with a tool like gerbv and check that:
- each layer looks more or less like what you'd expect. I'm not looking
for little things but gross errors like "hey, I thought layer 2 was
supposed to be largely solid ground but there is only 1 tiny trace".
- look for silk over solder mask relief. This should be a DRC check,
but it gets missed sometimes.
- scan over your drill table and make sure the sizes seem reasonable.
- for your ground/power plane layers or any other larger polygon fill
regions make sure that
a) there are some pins or vias that pierce the plane and do *not*
connect to it.
b) there are some pins or vias that *do* connect to it.
- are the plane layers pulled back from the mounting holes
- are the plane layers pulled back from the board edge
- if you have some large pin count footprints that you haven't used
before, measure distance between the corner pins and make sure that
matches the datasheet. Common offenders are QFN, QFP, etc. For
example, TQFP packages come in 0.4 mm, 0.5mm, and 0.65 mm pin pitch (at
least) so when you say '64 pin TQFP' that isn't enough.
- spot check any controlled impedance lines if you didn't do the layout
yourself.
- did you remember to include mounting holes?
Hope this helps
-Dan
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