Re: gEDA-user: Symbol style recommendations

[Steven Michalske <smichalske@xxxxxxxxx>]

On Mar 19, 2009, at 8:41 PM, Mark Rages wrote:

> 2009/3/19 Peter TB Brett <peter@xxxxxxxxxxxxx>:
>> On Thursday 19 March 2009 21:58:59 Josh Jordan wrote:
>>> I prefer to use actual pinouts in my schematics for two reasons:  
>>> It helps
>>> you with chip placement because naturally you will tend to place  
>>> symbols
>>> and lines to get the fewest line crossings.  Going to layout after  
>>> you have
>>> already decided the best general position for parts makes it much  
>>> easier.
>>> The second reason is that later on it will be easy to look back to a
>>> schematic that has a similar layout as the board and the same  
>>> pinouts.
>>
>> We'll have to agree to disagree. When I look at a schematic, I want  
>> to be able
>> to quickly and easily work out what the circuit is designed to do,  
>> and having
>> the pins on my symbols arranged by function and bus offset rather  
>> than by
>> physical position helps a great deal.
>>
>> What you're doing completely defeats the point of having separate  
>> schematic
>> and layout diagrams, IMHO.
>>
>> What do you do about parts that have different pinouts depending on  
>> what
>> package they're in?
>>
>>                                    Peter
>
> Of course you use the place the part on the schematic with the pinout
> you are using.
>
> When you are troubleshooting a circuit with a scope or analyzer, it
> adds an extra decoding step to have the pin order scrambled.  And it
> really is annoying when you're trying to look at the schematic to see
> where your 64-pin micro has an unused pin free.
>
I always use a layout with proper netnames when working off of a  
board,  then got to the schematic for the general idea.

it's easy to find extra I/Os when you name its net spare_IO_x

selected them in the netlist and highlight them in layout,  really  
easy :-)   cause I hate counting pins or balls.


This argument works for low pin count parts, it fails with high pin  
count parts.


For FPGA's we make customized symbols when the pinout of the device is  
I/O mapped.



> The usual problem with having the pins in IC-order is this big rat's
> nest of wires running around the chip to get to the pin.  But a better
> solution than moving the pins around is using named nets / ports.
> This also helps make the intended function of the circuit more
> explicit.
>
> Regards,
> Mark
> markrages@gmail
> -- 
> Mark Rages, Engineer
> Midwest Telecine LLC
> markrages@xxxxxxxxxxxxxxxxxxx
>
>
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