Re: gEDA-user: PALs GALs and SPLDs going the way of the Dodo?

[Ormund Williams <ormundw@xxxxxxxxx>]

On Mon, 2009-03-30 at 18:29 +0200, Gabriel Paubert wrote:

> It also depends on your needs: if you think that you are going to 
> produce a large series, avoid them. For a one time run of a few
> units, why not if you find them through www.findchips.com or similar.  
> 
> > Do you use SPLD? What do you use to program them? How about
> > the ISP versions?
> 
> Have you had a look at Lattice (www.latticesemi.com), they still
> sell them on their online store (apparently through Mouser) and there
> are quite a few in stock. There are even some low power models
> still available at Mouser.
> 
I'm familiar with the Lattice parts but I like the Atmel ATF16V8BQL
better, 5mA idle, 20mA active at 5v.

> ISP versions are nice for somewhat complex designs, when you already
> have a JTAG chain on your board and think that you might need 
> reprogramming them to fix bugs; obviously real hardware designers
> never need this, bugs are purely a software concept :-)
> 
> Besides that, at least from Lattice, only the ispGAL22V10A is worth 
> considering, the non-A need over 100mA even when idle. The A version 
> exists at 1.8, 2.5, and 3.3V supplies in a 32 pin QFN package (5x5mm). 
> Mouser has some of them in stock. 
> > 
Atmel and Lattice seem to be the only ones left, just looking at the
date of the last revision of the data sheets tells you that nothing has
happened in that sector since the late '90s.

> No problem, I'm also a bit fed up that there is virtually
> nothing left between bus buffers and multimillion gate FPGA
> which need 3 power supplies. I don't mind occasionally using
> a hammer to kill a fly, but using a nuke is too much and users
> complain from radioactive fallout :-). 
> 
> For very simple things (a Schmitt-trigger to drive a status 
> LED here and there in the middle of an analog design) I use 
> 1G series but they are not dense in terms of supply/ground 
> pin per gate so routing becomes a nightmare or 4 layers+ 
> are needed.
> 
I lost some of the space I had set aside to put the quad gates so I'll
use the 16V8 because I don't have the time to redo the entire layout.
This will probably be the last design I do with SPLDs, all I needed was
some logic to prevent shoot-through in the H-bridges and some way to
disable all the transistors even if the processor has gone of into the
weeds.

Change is inevitable, progress is not.

__
Ormund





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