gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?

[Patrick Doyle <wpdster@xxxxxxxxx>]

   Hello gEDA-ites... it's been a while since I've hung out on this list,
   but I'm glad to see you're all still alive and kicking :-)
   I have an Icarus Verilog question (which may, perhaps be a more
   general Verilog question).  I would like to write a test bench that
   exits with a non-zero status when it detects an error.  That way I can
   simply run make to test a bunch o' code and come back later to see if
   everything exited cleanly.
   Is there a way to exit the simulator with a non-zero status?
   I've asked my good buddy Google about this, but haven't figured out
   the right way to ask the question.  So I'm asking folks who are
   smarter than my buddy now :-)
   Thanks...
   --wpd


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