Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?

[Patrick Doyle <wpdster@xxxxxxxxx>]

   On Tue, Mar 3, 2009 at 11:50 AM, Larry Doolittle
   <[1]ldoolitt@xxxxxxxxxxxxxxx> wrote:

     Patrick -

     While functional, that technique still seems hackish.  The Icarus
     developers eventually added their own Verilog extension, the
     VPI function $finish_and_return(exit_status).  That will work in
     any development version since May 22, 2008.

   Oh... I like that!
   That's just what I was hoping my buddy Google would have found for
   me.  Should I have been able to find that somewhere else?  (I am
   asking in a tone of voice of "I would like to know where to look for
   answers such as these so I don't have to pester the mailing list" and
   not in a whiny tone of voice of "where's the docs?")

     On Tue, Mar 03, 2009 at 11:39:28AM -0500, Patrick Doyle wrote:
     >    I have an Icarus Verilog question (which may, perhaps be a
     more
     >    general Verilog question).  I would like to write a test bench
     that
     >    exits with a non-zero status when it detects an error.  That
     way I can
     >    simply run make to test a bunch o' code and come back later to
     see if
     >    everything exited cleanly.
     >    Is there a way to exit the simulator with a non-zero status?
     There is no standard way, so historically we used post-processing.
     Peek at the output for a "PASS" result, using a Makefile rule like:
     # Generic regression test
     %_check: %_tb testcode.awk
            vvp $< | awk -f $(filter %.awk, $^)

   Recently, I have discovered the beauty of Ruby, and of Ruby's make
   utility called "Rake", which allows one to use the full Ruby
   interpreter and available libraries from within a Rakefile.  (So one
   could write the code to check the output right within the rule itself,
   or define a procedure that could be called from other rules, or create
   a new "library" function that could be invoked by multiple different
   Rakefiles, etc...)  I was trying to convince myself that I should go
   back to traditional Makefiles for this new verilog project, but you
   may have just given me the (very little) push I needed (desired) to
   use Rakefiles instead.
   Thanks for the help.
   --wpd

References

   1. mailto:ldoolitt@xxxxxxxxxxxxxxx


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