Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

Patrick -

On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
>      developers eventually added their own Verilog extension, the
>      VPI function $finish_and_return(exit_status).
> 
>    Oh... I like that!
>    That's just what I was hoping my buddy Google would have found for
>    me.

It's tough to ask Google for something you don't know the name of.
Maybe they're working on that.  ;-)

>  Should I have been able to find that somewhere else?  (I am
>    asking in a tone of voice of "I would like to know where to look for
>    answers such as these so I don't have to pester the mailing list" and
>    not in a whiny tone of voice of "where's the docs?")

That function/extension was extensively discussed on the mailing
list.

http://sourceforge.net/mailarchive/forum.php?thread_name=20080522154426.GA3860%40recycle.lbl.gov&forum_name=iverilog-devel

I don't see it documented anywhere.  Maybe it should go in
extensions.txt?

   - Larry


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