Re: gEDA-user: Icarus Verilog: How to exit simulator with non-zero status?

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

Patrick -

On Tue, Mar 03, 2009 at 11:39:28AM -0500, Patrick Doyle wrote:
>    I have an Icarus Verilog question (which may, perhaps be a more
>    general Verilog question).  I would like to write a test bench that
>    exits with a non-zero status when it detects an error.  That way I can
>    simply run make to test a bunch o' code and come back later to see if
>    everything exited cleanly.
>    Is there a way to exit the simulator with a non-zero status?

There is no standard way, so historically we used post-processing.
Peek at the output for a "PASS" result, using a Makefile rule like:

# Generic regression test
%_check: %_tb testcode.awk
	vvp $< | awk -f $(filter %.awk, $^)

where testcode.awk is
---cut here---
# very general processing of vvp output to set a return code
# since apparently Verilog running inside vvp does not have
# a way to affect that directly
BEGIN{code=1}
/PASS/{code=0}
{print $0}
END{exit(code)}
---cut here---

Assuming you can get your simulator to save the results to stdout
or a file, this is about as general-purpose as it gets.

While functional, that technique still seems hackish.  The Icarus
developers eventually added their own Verilog extension, the 
VPI function $finish_and_return(exit_status).  That will work in
any development version since May 22, 2008.

   - Larry


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