Re: gEDA-user: gschem Bus tutorial

[Paul Tan <pt75234@xxxxxxx>]

Hi Ed,

In general, current gEDA architecturally supports any kinds
of BUS implementation. Specifically, current Gschem/Gnetlist
Verilog netlister supports simple BUS, e.g., data_bus[31:0],
etc., including true hierarchy. An example to demonstrate
"gEDA hiearchical Verilog design with bus" has been posted:

http://archives.seul.org/geda/user/Jan-2009/msg00056.html

However, most other backends, such as PCB, has not yet
implemented BUS in netlisting. PCB Netlisting with BUS
support can be implemented using similar strategy as
Verilog Netlisting.

In essence, the answer to your question depends on which
backends tools you are using.

Best Regards,
Paul Tan



-----Original Message-----
From: Kingston Co. <freddie@xxxxxx>
To: geda-user@xxxxxxxxxxxxxx
Sent: Sun, 29 Mar 2009 5:47 pm
Subject: gEDA-user: gschem Bus tutorial



Is there a tutorial anywhere?
I cannot find any detailed info on how to use this tool.

Thanks,
Ed
Kingston Co.
freddie@xxxxxx




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