Re: gEDA-user: pcb DRC

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Fri, 2010-03-26 at 16:00 +0100, Stephan Boettcher wrote:
> Duncan Drennan <duncan.drennan@xxxxxxxxx> writes:
> 
> > Double-clicking moves the cursor to the violation.
> 
> Yes, absolutely wonderful. 
> 
> Except, ... it centers the cursor on violating entity, and does not show
> the second entity that violates the clearance.
> 
> I've got 14 DRC violations left mostly on the power plane, that I cannot
> figure out what it is complaining about.  Might be false positives.  It
> highlights and centers on a polygon.
> 
> This is the board:
> 
>  http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
> 
> Any idea if it is a good idea to just ignore these violations?

Depends on how close to your fab's tolerance is. I see you have spacing
set to 8mil. Does the DRC pass as 7.9mil (no, it doesn't).

The first four violations I found (and was able to fix quite quickly)
relate to plane-plane gaps not being big enough in certain areas. The
DRC GUI doesn't have good information about where the violation occurs
in this case.

IIRC, the DRC works by shrinking or bloating individual elements in the
PCB, and looking for connectivity changes that (might) introduce. IE..
if bloating a pad by 8mil shorts it to something else... DRC violation.
It doesn't compute exactly where that short would have occurred. (e.g.
where the gap is too small).


Some tips for easier DRC problem identification:

Select the silk layer as your active layer (required for the next step),
then de-select all the copper layers and run the DRC.

Clicking on a violation will re-enable affected layers, so the objects
in question are _much_ easier to identify. De-select all layers before
moving onto the next violation.

Regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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