-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Am 26.03.2010 16:34, schrieb Peter Clifton: > > > Some tips for easier DRC problem identification: > > Select the silk layer as your active layer (required for the next step), > then de-select all the copper layers and run the DRC. > > Clicking on a violation will re-enable affected layers, so the objects > in question are _much_ easier to identify. De-select all layers before > moving onto the next violation. > > Regards, > Hi, I think I have a similiar problem of false error indications> The attached board shows 1 DRC error: "Pad with insufficient clearance inside polygon". The pad and the polygon are in different layers withein the same layer group, so they will show up on the same 'physical layer' (same plane of the board), where I do not see an insufficient clearance. Related to that, I'm not able to put a thermal to any pad (pad is on component layer, polygon is on power layer, both are in the same layer group). What is a good suggestion to create power / gnd polygons on a double sided board? Use the power/GND layers and assign them to a layer group or create power/GND polygons on the component / solder layers? I plan to release the board next week and will disregard the DRC error after inspecting the Gerbers carefully. - -- Mit freundlichen Gruessen /Best regards Dietmar Schmunkamp -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.12 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org/ iEYEARECAAYFAkutUnsACgkQn22l+QvEah1r5ACdFO+IBXbutgcq3EcuqJRrG7am EuAAn3QszOy6qAa4LIEL4R20bvrNQlwX =jl9V -----END PGP SIGNATURE-----
Attachment:
bikepower.pcb
Description: application/pcb-layout
_______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user