Re: gEDA-user: pcb DRC

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Sat, 2010-03-27 at 01:34 +0100, Dietmar Schmunkamp wrote:

> I think I have a similiar problem of false error indications>
> 
> The attached board shows 1 DRC  error:
> "Pad with insufficient clearance inside polygon". The pad and the
> polygon are in different layers withein the same layer group, so they
> will show up on the same 'physical layer' (same plane of the board),
> where I do not see an insufficient clearance. Related to that, I'm not
> able to put a thermal to any pad (pad is on component layer, polygon is
> on power layer, both are in the same layer group).
> What is a good suggestion to create power / gnd polygons on a double
> sided board? Use the power/GND layers and assign them to a layer group
> or create power/GND polygons on the component / solder layers?

Personally, I don't use layer groups, as I don't really see the point.
It usually means yet more colours on an already complex design, it is
harder to visualise what copper is on what layer..

And you can't even turn the sub-layers within a layer group on/off, so
it isn't even useful to hide polygons temporarily.


It is possible there is a bug in the DRC relating to layer groups.. if
you can identify something with a minimal test case (showing how it
fails with multi-layers in a layer group, but passes DRC on a single
layer), please file it on Sourceforge so it doesn't get forgotten.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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