Re: gEDA-user: pcb DRC

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Sat, 2010-03-27 at 08:57 +0100, Stephan Boettcher wrote:
> gene glick <carzrgr8@xxxxxxxxxxxxx> writes:
> 
> >> This is the board:
> >>
> >>  http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
> >>
> >> Any idea if it is a good idea to just ignore these violations?
> >>
> >
> > Blindly ignoring violations is probably not a good idea.  Better to
> > understand them first.
> 
> Well, I visually scanned the perimeter of the violating planes and did
> not find any problems, OTOH, Peter did see them, he said, so I need to
> look more carefully.

I didn't verify whether they were in fact, too close, just that I could
make the violations go away by adjusting their clearances. It could be
that PCB is miss-calculating the gaps.

It is also possible that the points which get too close aren't actually
visible - are cleared away by vias / tracks - but the DRC check is
"imagining" what the polygon is defined to look like when checking it
against other polygons. I'm not 100% sure on that.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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