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Re: gEDA-user: pcb DRC
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Am 27.03.2010 12:21, schrieb Peter Clifton:
> On Sat, 2010-03-27 at 01:34 +0100, Dietmar Schmunkamp wrote:
>
>> I think I have a similiar problem of false error indications>
>>
>> The attached board shows 1 DRC error:
>> "Pad with insufficient clearance inside polygon". The pad and the
>> polygon are in different layers withein the same layer group, so they
>> will show up on the same 'physical layer' (same plane of the board),
>> where I do not see an insufficient clearance. Related to that, I'm not
>> able to put a thermal to any pad (pad is on component layer, polygon is
>> on power layer, both are in the same layer group).
>> What is a good suggestion to create power / gnd polygons on a double
>> sided board? Use the power/GND layers and assign them to a layer group
>> or create power/GND polygons on the component / solder layers?
>
> Personally, I don't use layer groups, as I don't really see the point.
> It usually means yet more colours on an already complex design, it is
> harder to visualise what copper is on what layer..
>
> And you can't even turn the sub-layers within a layer group on/off, so
> it isn't even useful to hide polygons temporarily.
>
>
> It is possible there is a bug in the DRC relating to layer groups.. if
> you can identify something with a minimal test case (showing how it
> fails with multi-layers in a layer group, but passes DRC on a single
> layer), please file it on Sourceforge so it doesn't get forgotten.
>
Peter,
thanks for your answer.
I think I got to the root cause of my problem:
The pad has a width of ~16 mil and I used the autorouter to connect it.
I set the trace width to 8mil with 8 mil gap. So I got a trace to the
pad with 8 mil width on the "north" side of the pad (not in the center
of the pad). As this particular pad is the power pad I wanted to connect
it with a wider trace (for cases where the trace is centered, I simply
widened the trace), so I tried to (ab)use a polygon for that. While I'm
able to connect a net to a polygon (using the join command), this is not
possible for connecting a pad to a polygon. I have a circumvention for
this: create the polygon with the correct gaps and use a parallel wire
to connect the pad to the polygon.
To make a long story short:
I stumbled over a feature of the DRC.
I have a circumvention for that.
Fixing my particular problem of detecting a false positive would hide
possible real errors (my problem was a DRC error to a plane the pad was
already connected to, but in general the DRC check is valid for any
I'll change my board to have all shapes (nets and polygons) on the same
layer. With my setting of having the polygons on an extra layer I'm not
able to place thermals. When trying this, the command is simply ignored.
I remember previos versions of the DRC to highlight one net in the
"found" colour and the offending net in the selected colour. I'm missing
that for the latest version.
I'm going to send out the board to manufacturing monday or tuesday, I'll
post here if the manufacturer (www.haka-lp.de) has problems with the
generated gerbers. The manufacturer seems to be Eagle-centric, but
accepts RS274-X as well.
I like the DRC within PCB very much, but as a final check I'd like to
have a DRC check on gerber data (that's all the manufacturer gets), so
does anybody know whether there is a tool that's provides such a check?
I loaded the gerber files into gerbv and did a manual check, but an
automated check would be better, There must be some (possibly $$$)
programs to do that, or how do the manufacturers provide feedback to
theier customers?
- --
Mit freundlichen Gruessen / Best regards
Dietmar Schmunkamp
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