Re: gEDA-user: pcb DRC

[Stephan Boettcher <boettcher@xxxxxxxxxxxxxxxxxx>]

Peter Clifton <pcjc2@xxxxxxxxx> writes:

> On Fri, 2010-03-26 at 16:00 +0100, Stephan Boettcher wrote:
>> This is the board:
>> 
>>  http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb
>> 
>> Any idea if it is a good idea to just ignore these violations?
>
> Depends on how close to your fab's tolerance is. I see you have spacing
> set to 8mil. Does the DRC pass as 7.9mil (no, it doesn't).

I set DRC to 8mil/8mil, routed with 10mil, and mostly kept 9mil clearance.

The planes are all done on a 5mil grid with at least 10mil spacing.  I
really cannot see where that fails.  Maybe its some kind of illusion,
that the gaps on diagonal parts appear bigger, but are in fact closer
than 8mils?

> The first four violations I found (and was able to fix quite quickly)
> relate to plane-plane gaps not being big enough in certain areas. The
> DRC GUI doesn't have good information about where the violation occurs
> in this case.

Thanks,  well, I will look at that again.

> IIRC, the DRC works by shrinking or bloating individual elements in the
> PCB, and looking for connectivity changes that (might) introduce. IE..
> if bloating a pad by 8mil shorts it to something else... DRC violation.
> It doesn't compute exactly where that short would have occurred. (e.g.
> where the gap is too small).

-- 
Stephan


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