Re: gEDA-user: General Layers questions

[Stephan Boettcher <boettcher@xxxxxxxxxxxxxxxxxx>]

Martin Kupec <martin.kupec@xxxxxxxxx> writes:

> On Wed, Mar 16, 2011 at 02:42:26AM +0100, Stephan Boettcher wrote:
>> IMHO, .. holes are circles draw on just another layer.  People were
>> asking for slots.  If they find a vendor to do them, they may just draw
>> lines on that layer as well.  Else, DRC shall flag non-circles.
>> 
>> Each such hole layer shall have a spec (attribute) to which (copper)
>> layers they electrically connect.  There will be at least one such layer
>> for each type of blind, burried, and through via.
>> 
>> The GUI will happily stack vias according to the selected routing style
>> into a composites and paste them on the layout, so for simple cases
>> nothing changes from how we work now.
>
> Ok. So "via" should be a circle element on "hole" typed layer.

No.  A Via is a composit, consisting of a circle on the hole layer, and
various circles on copper layers, and circles on mask layes, and
thermals.

A library (routing style) Via would have top, inner, (outer?), bottom
copper layers, which would be mapped to physical copper layers of the
layout according to some mapping, exactly as for footprints.

In addition, some projects would have their own sets of Vias in a
library, where those circles are expressed explicitly for the physical
hole/coper layers of that board, for burried and blind vias, or special
annular ring config on certain inner layers. That library shall be
linked to some Via GUI to efficiently choose from.

> That object will have some description to which "layers" of type cooper it
> belongs to. 

The hole _layer_ should have that description.  The default connects to
all copper.  Blind and burried vias require extra hole type layers, one
for each set of drill stacks.  This information is needed for
connectivity checks mostly.  Some DRC check may verify if the drilling
of the stacks is feasible.

I think this is simpler and more flexible that DJs proposal: to
hierachically group (copper) layers into drill stacks.  That would be a
John D violation, since it originates from a narrow view on how PCBs are
manufactured.  It in no problem to reflect such a narrow view in a DRC
rule, but it is a mistake to cast it into the core data structure.  A
HID may present the layers in such an arangement to the user. Said HID
may then proceed to add the required hole layers and Via types
automatically, after the user pushed the copper layers around as
required for the project.

> And how would you describe the cooper around via on each layer?
> Someone wanted different cooper size/shape on different layers.


> 	Martin Kupec

-- 
Stephan



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