On Tue, 2011-03-22 at 10:51 +1100, Geoff Swan wrote: > > Lots is possible, but I'm not sure how you would best go about > it. > gEDA's bus support is almost non-existent... it is just a > graphical > nicety, and relies upon named nets. (I vaguely recall that > Altium buses > can work like this too if you want) > > I haven't really used busses properly in Altium - as you described, > I've primarily used them just as a graphical nicety while explicitly > naming all the connected nets. There may have been a few cases where I > named the bus and then connected nets were given the bus prefix, or > something like that. But at the time I was just experimenting and > didn't really need or find this sort of functionality added much > value. (I imagine with a number of 32/64 bit busses something that > removed the need to individually name nets would be handy though) > > In terms of the channelisation functionality my current thought is > that I may be able to augment the gnetlist pcb backend to recognise > something similar to a bus notation and recognise when a > symbol/subcircuit needs to be replicated. (btw - I haven't yet started > looking through the gnetlist backend sourcode or doco so if this > sounds like something impossible - feel free to give me a heads up :) It might be possible, but I'm not as familiar with gnetlist as with other parts of the suite. I mostly do rendering / UI stuff (in gschem and PCB). I vaguely recall that the verilog backend does something with nets named "something[12-9]" (or whatever the verilog bus syntax is), but that just maps onto the data-types used when producing the netlist, not the structure of the schematic. I'm fairly sure you cannot dynamically instantiate channels within gnetlist though (short of implementing a lot of hackery in the netlist backend). When I've done channels in the past, I've kept them on separate schematic pages, then used a makefile and some simple bash / sed / awk scripting to increment component numbers and spit out each channel as a new page. I would then create a symbol which represents all the channels (in a hierarchical design), then wire that into the schematic. If we supported buses properly, this could even be done with bus pins - but we don't at present. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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