Re: gEDA-user: General Layers questions

[John Griessen <john@xxxxxxxxxxxxxx>]

On 03/19/2011 12:01 PM, Martin Kupec wrote:
> > > On Sat, Mar 19, 2011 at 10:14:54AM -0600, John Doty wrote:

> > > No problem here. Just define that conductive ink as copper or conductive
> > > >  >  type layer. I don't care how that layer happens to be manufactured.
> > >
> > >  No. For describing geometry, I agree that the manufacturing process is
irrelevant. But the layer needs properties, not some arbitrary classification.
> I never said that you cannot add additional properties(attributes) to
> the layers. I am just saying that there should be some, as you say,
> arbitrary classification. And than you refine that clasification by some
> properties. But the basic classification will be clean and understood by
> all parts of pcb. The additional properties can be admited just by some
> parts.

I also like to keep the data structures aligned with a physical reality as in
properties attached to layer data that represents physical stack up existence.

Defining steps in manufacturing processes gets too way off in the unknowable to be workable
on a FOSS project.  Just defining what is there is really big and bogs down chip designers
if they let it, so we need to watch out for it as board designers.  Boards will look like
chips soon enough.  Any time you consider defining something by a process, such as
hole making, you could instead define where material is in a 3D pixel and an attribute
is fine for that.

A stack-up layer is not the same as a physical layer, since physical
material can fold and compress as layers are processed.  For instance
solder mask -- it flows over etched conductive layer
material until it can make the silkscreen print fill differently because
it is no longer in a planar layer, but a rumpled non-flat but continuous layer.
I think the stack-up of non-flat material is something we should plan for
some, but put off mostly right now.
It's a tough problem.

Allowing that a stack-up layer could have several different materials
in it is current technology that is evolving quickly, so we want that.
Saying the we can model physical stack-up that distorts a little and stays
mostly planar with an error is something we can plan for now and
get a big benefit.  A stack-up layer wouldn't be complete if it was
a hole definition layer, and you can derive the  hole def layer from stack-up,
so use the word layer to mean a model of physical material that is somewhat
flat, with errors less than X away from being a stack of cubic pixels.
That way is bottom up as John Doty recommends and allows extracting physical
model data from simulation for more benefits.

On 03/18/2011 06:34 PM, Stephan Boettcher wrote:
> Still, I do not see a need for outline layers anywhere, except as an
> attribute on a graphical layer that tells an exporter where to stop
> drawing.

I agree that outline as it is done now is not consistent with the above plan.
The function of outline for routing or extent of the board you are
designing could be handled by an attrib on a trace.  To be consistent
with modeling physical material, the outline trace (or future 3D pixel)
should be outside the edge of material
that is kept rather than its centerline defining that edge as it is done
for outline definition RS274-X files.

Even using outline attrib to create an edge is a negative space definition
that could be skipped.   Instead, you could define
all the intermediate physical FR4 composite or printed material including its
extent being a non-default, non-rectangular presence of material.  We now
define FR4 composite material only indirectly.  Besides streamlining the whole
way of representing stack-up materials, additive processes will
naturally demand insulator materials that go down as "printed layers", just
as solder mask, copper, silk-screen do now.  Once you go all the way to defining
presence of material as your basic model, you no longer need any definers
of negative space...


John Griessen


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