Sorry for the long delay in responding, I've been quite busy.
I've attached my Super OSD layout PCB, which is open hardware.
However, here's a more detailed description of the problem. In
particular, if I delete the trace causing the error, it will find
another error which it did not find before. Try it yourself. Run DRC,
delete the offending trace, run it again.
On 21 March 2011 08:19, Peter Clifton <[1]pcjc2@xxxxxxxxx> wrote:
On Mon, 2011-03-21 at 00:01 +0000, Thomas Oldbury wrote:
> Been playing around with the current git release 1.99z (probably
> unstable?) and I've noticed there is one bug - it always wants to
> complain about a DRC error, no matter if the board is clean. In my
> case, the error seems to be chosen randomly from a perfectly good
> trace, and is almost always a "copper areas too close" error. I'm
using
> 6/6 mil rules and this is a 44pin 10mm TQFP, as can be seen, the
trace
> has more than adequate clearance. (The other DRC error is due to
some
> dead copper I think, but nothing to be really concerned about.)
Can you send an example layout file which shows the problem?
I wonder if the image preview is just a little shifted from what is
really causing the problem. In the screen-shot you showed, the plane
clearance near the via just above what looks like the word "core",
to
the bottom track shown in your DRC violation looks a little close.
The "too close" and "insufficient overlap" DRCs work by
systematically
bloating or shrinking geometry, and looking for any shorts or open
circuits that might cause respectively.
I can't remember exactly, but it might also be triggered by a line
segment which doesn't have the required clearance set on it, even
though
it is not shorting against anything else (perhaps because planes are
cleared away by other objects with bigger clearances).
Best wishes,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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Attachment:
pcb-v3.25-lite-199z-with-no-tenting.pcb
Description: application/pcb-layout
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