Re: GPLd PCB Library ( was Re: gEDA-user: Free GNU/Linux hardwaredesign tools)

[John Griessen <john_g@cibolo.com>]

On Wed, 2003-05-14 at 02:23, John Dalton wrote:
> calculates everything
> based on package dimensions and solder joint properties.  Are there any
> more factors you are aware of?


How about the factor of heat dissipative surface area desired for some
devices?  Power MOSFETs are packaged carefully to put minimum heat
conduction resistance into the heat flow path out of the package, and so
the recommended pad footprints often have only partial
surface-tension-leg-locating shapes for their pads, and have a wide
rectangle of pad metal leaving one side of the area of a tab or leg.  
You could just treat them generically and let the designer put extra
metal on, but that would lessen your built in checking and "known
goodness" of pad footprints.

Another factor from a new package type:  There is also a new power
packaging process that even IPC-SM-782A may not have it's so new...(I
need to read IPC-SM-782A, don't I?).  The new way I read about is a die
with raised metal bumps on the silicon substrate, passivation glass
thicker than usual on the rest of the die, and a metal backing on the
non-active backside of the silicon wafer substrate.   The die attach
pads are meant to contact solder paste zones on signal pads, and the
metal backing plate is meant to contact solder paste on
heat-flow-grounding-shielding metal.  The chip attach bumps are going to
be smaller by a good bit than some package legs.

Thanks for making something like this.  Can we look over your shoulder?
What language are you coding it in?  What VRML viewer?
What form is your 2D output?  Can you see making 2D output in XML-SVG,
the supposed new illustration language of the web?

John Griessen
green power conversion and lighting electronics and systems