Re: gEDA-user: Assertion based verification using VCD and VHDL

[Ales Hvezda <ahvezda@moria.seul.org>]

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-- Cut here --
From: Darryl Dieckman <ddieckman@cliftonlabs.com>

Peter Kaiser wrote:
> Hi, 
> 
> I also work on a open source tool chain for mixed signal asics. Unfortunatly I 
> don't know a tool that converts VCD to VHDL or Verilog.  My ASIC's are 80% 
> analog with only a small digital part to control e.g. SC amplifier.
> May I ask you 2 questions: 
> - What Spice do you use?
> - How do you come from Spice output (raw) to vcd?
> 


The design that we are working on is about 50% digital and 50%
analog.  We typically use spice3f5 or ngspice to do simulation.
Right now I use a Perl script that I wrote to convert .raw to
.vcd and then I use gtkWave to visually inspect the signals.
I am cleaning up the Perl script and plan on GPL'ing it as
soon as I can.

Darryl