[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: Re: Composite/negative layers in gerbers



On Fri, 2006-05-05 at 07:21 -0700, Paul Kube wrote:
> I made all layer names unique and resubmitted the job to OLIMEX.
> 
> Their reply: 
> 
> "every decent cad product can generate copper pour with hatch stroke fill
> the negative plot is ancient way to make copper ground back in the ages 
> when computers had no power to calculate the stroke fill coordinates
> we can't handle your order if made with composite layers"

<MY 0.02>
Ahem... As a case in counterpoint to Olimex's statement, Mentor Board
Station and Cadence Allegro, which are arguably decent, albeit costly,
products both use negative layers the same way that PCB does.  We use
negative layers all the time for our power planes, it's much simpler and
less error prone to flash the pad images out of the negative layer and
cut up the plane with traces than to do the hatching.  Although you can
flood fill if you have to, just be prepared to have lots of spare CPU
cycles and RAM.
</MY 0.02>

> 
> So, apparently they mean the same thing by 'composite layers' and 
> 'negative plots', namely the use of LPD and LPC on the same layer.
> 

I believe that PCB uses the following logic to output `negative' planes:

	1) If there is a single polygon covering most of the plane use a
negative image. Emit commands to flash holes in the plane for via
clearances and thermals.

	2) If there is even a single trace drawn on the layer, use the
paint/scratch/paint method.

So, to get PCB to output a positive image for a plane, draw at least one
trace on that plane, along with your polygon and set the `line clears
polygon' flag to false.

As an aside, I wonder if Olimex actually using a real honest to goodness
photo plotter? (The kind with XY stepper motors and a light bulb with
apertures.) If so, then the paint/scratch/paint won't work.  Exposing
film is a one way process.

> --Paul
> 
-- 
--------------------------------------------------
                              Mike Jarabek        
                                FPGA/ASIC Designer
  http://www.istop.com/~mjarabek                    
--------------------------------------------------