Re: gEDA-user: stupid divider

[Dan McMahill <dan@xxxxxxxxxxxx>]

Rick Collins wrote:
> Rather than a poorly formed edge, your results can also be explained 
> by wiring the chip wrong.  For example, if you had the set input tied 
> low and the clock on the reset line, I think it would give you 
> exactly what you are describing.  IIRC, the reset has priority over 
> the set input, so the low clock half will force the output low.  Then 
> when the clock is high, the output will rise again due to the set 
> input being wired low.

quadruple checked, even after walking away and coming back the next 
morning.  Even checked more than one vendors datasheet as a sanity check.


John Luciani wrote:
 > NB: Before Cappuccino Guess

this whole thing is making me question giving up coffee many years ago.

 > What is the minimum guaranteed hold time and minimum
 > propagation delay for the part you are using?

The min prop. delay is with a moderately large load, more than I had. 
Upon checking several vendors datasheets, it seems there is a moderate 
variation in the hold time.  It still looks like I should have had 
margin.  So to hit it with a larger hammer, I ran the feedback signal 
through several inverters from a slower logic family to really ensure 
there was absolutely no question of hold time violations.  No improvement.

 > I am wondering if a small load (50-100pF) on the output of the /Q would
 > get you well beyond any potential hold time issues.

didn't work.


Ben Jackson wrote:
 > On Sat, May 03, 2008 at 02:38:51AM -0400, Dan McMahill wrote:
 >> The signal I'm trying to divide is down in the handful of kHz range and
 >> the only reason I'm using 74ACT instead of something like 74HC is thats
 >> what I had in the parts box in the basement.
 >
 > There's a minimum edge rate of 125mV/ns in this datasheet (from 0.8 
to 2V,
 > so about 10ns).  Are you meeting that?

I saw that and was concerned that at first I may not have been (no way 
to tell at first due to limited bw scope).  So I did some conditioning 
of my clock to where I should have easily been meeting this.


 > Also, ACT requires 5V, you can't run it on 3V like you could AC.

It was running from 5V.

 >
 > If you had a really long input line and a very fast edge I would wonder
 > if the clock was ringing enough to trigger a second transition.

My clock line is pretty short, but I've about concluded there is no 
other explanation (unless I have some zapped parts but I don't any more 
to swap out).  A ring that caused the ff to be clocked on the falling 
edge as well as the rising edge would, I think, explain everything I've 
seen.  Still I'm disturbed because I tried a few things which should 
have changed that a little.

I think what I'm going to do with that board is take it over to a 
friends house where there is a real lab with scopes fast enough to 
really verify things like ringing on the clocks, clock slew rate, and 
hold times (set up times are so incredibly long that I have orders of 
magnitude of margin).


In the mean time, I dug through my lucky box o' parts and found some 
different style flip-flops from a slower speed logic family.  60 seconds 
of plugging it into a proto board and it works.  At least I feel better 
about that.

All this just to drive a stepper motor from an old printer so I can keep 
some expoxy from sagging while drying....


-Dan



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