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Re: gEDA-user: stupid divider
Rather than a poorly formed edge, your results can also be explained
by wiring the chip wrong. For example, if you had the set input tied
low and the clock on the reset line, I think it would give you
exactly what you are describing. IIRC, the reset has priority over
the set input, so the low clock half will force the output low. Then
when the clock is high, the output will rise again due to the set
input being wired low.
Check the data sheet for the part you are using. I don't recall if
different families of TTL parts are pinned out differently or
not. Also, be sure you are using the correct pinout for the exact
package you are using. I know that some footprints are pinned out
differently.
Rick
At 02:38 AM 5/3/2008, you wrote:
>As long as we're on electronic circuits instead of CAD tools a bit
>today, here's a simple question. Has anyone else had problems getting a
>simple divide by two with a 74ACT74 to work? Its a pretty darn simple
>circuit. D flip-flop, set and reset tied high (both are active low),
>Qbar connected to D, clock applied to the clock. The part is on a
>protoboard with a solid ground plane. It's heavily bypassed as close as
>one can possibly get and then bypassed even more still pretty close.
>The other half of the chip is also set up as a divide by 2 with its
>clock input being driven by the output of the first half.
>
>The stupid thing just doesn't seem to work. I'm getting the same thing
>out of Q as I put in on the clock. The part has a positive clock to q
>delay (as I should hope it would!), and has a negative hold time so all
>told I should have a handful of nanoseconds of timing margin. Setup
>time should be a complete non-issue since my input frequency is well
>below the max toggle rate of this part (by orders of magnitude). I was
>worried that perhaps I didn't have a fast enough edge on the clock
>coming from my super low end square wave generator so I made a simple
>schmitt trigger with some inverters in a 74ACT04 and then ran that
>through a few more inverters so I should have a clean edge (at least
>free of glitches) that is fast enough. My interconnect is all very very
>short.
>
>To within the limits of my 65 MHz scope (yeah I know its not quite
>enough) the applied clock looks clean.
>
>The signal I'm trying to divide is down in the handful of kHz range and
>the only reason I'm using 74ACT instead of something like 74HC is thats
>what I had in the parts box in the basement.
>
>It looks to me like somehow I'm getting a spurious clock rising edge as
>part of the high to low transition. I don't see it on the scope, but
>that would explain the Q/Qbar outputs I see from the first divider. The
>second one has the same problem. Again, my clock should be fine. In
>fact the clock is the output of the first divider.
>
>There is nothing else on the board. I don't have any floating inputs of
>unused gates around. I even changed the chip.
>
>There's nothing so frustrating as when the simplest of circuits don't
>behave!!!! I keep thinking I must be doing something painfully stupid,
>but I just don't see it.
>
>Thanks
>-Dan
>
>
>
>
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