Re: gEDA-user: Support for busses

[Bill Cox <bill@viasic.com>]

Bill Cox wrote:

> Keith Outwater wrote:
>
> > > -- Busses get netname attributes of the form "FOO[3:0],BAR[2],ENWR". 
> > > Net's tapping busses is for visual apperance.  The connection to the 
> > > bus is implicit in the signal name that must appear on the net 
> > > somewhere anyway.   
> >
> > Yes, but what if you don't name the net?  Wouldn't it be nice if you 
> > could simply rip off a bus member using a 'rule' attribute and forget 
> > about having to name the ripped net?
> > Here's an example of why this is a Good Thing:
> > Let's say I create a schematic with four memory chips which connect 
> > to a 32 bit data bus named cpu_data[31:0].  On each chip, I rip 8 
> > bits from the bus.  Most schematic editors require me to name each 
> > ripped net: cpu_data[0], cpu_data[1], ...  Now this is a big hassle 
> > and does not add any useful information whatsoever to the schematic 
> > since I already know the bus name (it's cpu_data).  What happens now 
> > when I decide to change the bus name to local_data[31:0]?  You 
> > guessed it: everything has to be renamed.  This makes editing a pain 
> > and reuse a real pain.
> >
> > Instead of this drudgery, how about allowing a 'rule' attribute to be 
> > placed on a bus ripper to indicate the index of the bus member to be 
> > connected to the ripped net?  For example, if I want to rip 
> > cpu_data[4] off of the bus, I place a bus ripper on the bus and 
> > change the rule attribute to 4.  Whatever net I connect to the other 
> > end of the bus ripper gets connected to cpu_data[4].  Simple.  This 
> > approach completely avoids the redundant placement of bus names on 
> > the ripped nets and allows the entire bus to be renamed by changing 
> > the bus name in one place.  Obviously, there needs to be a net name 
> > resolution policy, but that's no big deal.  Better yet, if there is a 
> > net name conflict, pop up a dialog and ask the user what he wants to do.
> >
> > BTW, as far as I know, only Mentor's Design Architect gets this stuff 
> > right.  Maybe Cadence does too.  Then again both tools cost some real 
> > money.
> >  
> This sounds good to me.  How about if we let the user set the 
> "netname" attribute to a simple index, like "[4]"?  Then the full name 
> could be obtained from the tap.
Hi, Keith.

I want to implement the bus tap rules you suggest.  I went to go write 
the code and realized I don't have quite enough information.  In 
particular, busses can be multiple signals concatentated.  For example, 
a legal bus name is "A1,A2,A3,A4", or "a[7:0],b[7:0]".  If I simply put 
an attribute name on a bus tap like [4], then I assume that means the 
5th signal in the bus.  However, if the bus name is "a[63:32]", I would 
like to be able to tap signals with names like "[35]", rather than 
making them 0-based indexes.

How should I deal with this?  If you have a good scheme, I'll go write it.

Thanks,
Bill