Re: gEDA-user: Support for busses

[Svenn Are Bjerkem <svenn@bjerkem.de>]

On Saturday 08 November 2003 16:35, Bill Cox wrote:
> I want to implement the bus tap rules you suggest.  I went to go write
> the code and realized I don't have quite enough information.  In
> particular, busses can be multiple signals concatentated.  For example,
> a legal bus name is "A1,A2,A3,A4", or "a[7:0],b[7:0]".  If I simply put
> an attribute name on a bus tap like [4], then I assume that means the
> 5th signal in the bus.  However, if the bus name is "a[63:32]", I would
> like to be able to tap signals with names like "[35]", rather than
> making them 0-based indexes.

with [4], do you mean then that it is A4 above (in A1,A2,A3,A4) if it is one 
based? I don't see how you want to make the user aware that a signal is 1 
based or 0 based. 

Remember there are logical and physical busses in many designs. Cadence do 
make a difference between logical and physical busses. I havent quite grasped 
the difference in Cadence as I consequently use the <> bus declaration.

What I do recognize is a need to make simplified representation of complex 
signal collections. An example may be on the very top level of a chip or a 
module used in a chip, you want to have a human-readable bus name, say, 
control[15:0] which go between the two blocks uRom and Accu and consist of 
regtl<7:0>,regls<3:2,0>,regrt<9,7,5,3,1> which are the actual lines. (the 
names are made up for example only)

This way you don't need to change the top level bus if the local signal names 
change due to reusability. (I could use a different uRom module for the same 
Accumulator if the uRom happen to have other signal names) Care must be taken 
on the left to right assignment on each of the end of the busses, but that is 
also the reason why I use <> all the time in Cadence. (Also there are some 
netlisting errors if I use [])


-- 
Svenn