Ah, good, a critic. That means I might learn something!
On Mon, Nov 14, 2005 at 08:59:09PM -0500, Hal2000 wrote:
Larry Doolittle wrote:
I welcome constructive criticism [ of
http://recycle.lbl.gov/~ldoolitt/ft256/ ].
IMHO, you just can't get enough storage in a cap to supply the
instantaneous switching needs of a high speed IC.
That makes me nervous, too. I'd like to see some numbers for
the Spartan 3 to quantify this. How short is the current spike
on VCCINT when a "whole bunch" of logic cells clock? Do they add
some on-chip or in-package capacitance to give us half a chance?
The individual transistors probably spike in 10 ps, and a whole
logic cell in 100 ps.
If I ever have trouble on VCCINT, it has occurred to me that
I can fuss with pipelined logic to split the effort among different
clock edges, the goal being to spread the power supply transients in
time. 3 nC every 5 ns sounds easier to filter than 6 nC every 10 ns.
Assuming the feed is purely inductive, and the chip has non-zero
capacitance, the former case has half the power supply ripple.
Generally, this comes
from the power planes themselves. If you can get your power and ground
plane to within 0.002" of each other (pretty realistic these days),
Last time I asked board shops, they grimaced at anything under 3 mils.
That was over a year ago. I was figuring on something like a 5/5/40/5/5
stackup. My understanding is that a 6-layer board is made of
prepreg laminate prepreg laminate prepreg
so the key separator between layers 2 and 3 (Ground and Power) is laminate.
you will make the best capacitor possible. That doesn't mean you can skimp
on bulk capacitance, but remember it's the plane that supplies power for
the switching edges first. BTW, those long inductive traces you had
there for power will kill your chip at high frequency.
Define "long", "kill", and "high frequency". ;-) See above.
I can fatten up most of the power traces from 10 mils to 20 mils,
which will help a little.
One other point, something I noticed with the way you escaped your BGA.
Each ball has a short trace that aims inward toward the center of the
chip. In my experience, it usually goes outward. The benefit is a
larger routing area in the center of the BGA. You get a "+" looking
space, but if you aim you escapes inwards, the "+" is really thin.
Are we looking at the same board? Each ball (well, most of them) is
paired with a via, and the via is further from the center than the ball.
I do have a "+" looking space, and that's where I place eight 0603 caps.
Oh, your 6 layer board is not symmetrical. Check with your PCB vendor
to see if it'll warp.
I plan on symmetric ground planes, layers 2 and 5. Top and bottom, layers
1 and 6, look similar in density to me. Are you looking at the difference
between 3 and 4? Once the board is complete, I could add some copper
pour to even them out, if you (and the PCB vendor) think it would help.
- Larry