gEDA-user: Help needed running a test

[Stephen Williams <steve@xxxxxxxxxx>]

Hi,

I need help with this test from the ivtest test suite. The person
who wrote the attached test assumed that the always blocks near
the top of the example would eliminate pulses that are narrower
then the delays within the loop, but I'm not so sure that it
reasonable in this case. So I would like to know what the big
name tools do with the program.

Can folks who have access to the big Verilog simulators run the
attacked sample program and send me the output and VCD dump?

Thanks,
--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

module test ();

reg a,b;

always @(inp)
  a = #5 inp;
always @(inp)
  b = #3 inp;

reg inp,error;

initial
  begin
      $dumpfile("test.vcd");
      $dumpvars(0,test);
      #1 ;		// 1 ns
      error = 0;
      inp = 0;
      #6;		// 7 ns
      if(a !== 0)
         begin
            $display("FAILED - a doesn't clear to 0 at init");
            error = 1;
         end
      if(b !== 0)
         begin
            $display("FAILED - b doesn't clear to 0 at init");
            error = 1;
         end
      #1;		// 8 ns
      inp = 1;		// Create a 4 ns pulse 
      #4 ;
      inp = 0;		// 12 ns
      #4 ;
  end

initial 
  begin
      # 12;
      // We should see a as 0, and b as 1
      if(a !== 0)
         begin
            $display("FAILED - a propagated pulse early");
            error = 1;
         end
      if(b !== 1)
         begin
            $display("FAILED - b doesn't propagate pulse as expected");
            error = 1;
         end
      # 3; // 15 ns
      if(a !== 0)
         begin
            $display("FAILED - a propagated pulse and shouldn't ");
            error = 1;
         end
      if(error == 0)
         $display("PASSED");
    
  end
 
endmodule