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Re: gEDA-user: geda-gnetlist problem
$gnetlist -v -g spice-sdb -o TwoStageAmp.cir TwoStageAmp.sch
Command line passed = gnetlist -v -g spice-sdb -o TwoStageAmp.cir
TwoStageAmp.sch
gEDA/gnetlist version 20061020
gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details.
This is free software, and you are welcome to redistribute it under certain
conditions; please see the COPYING file for more details.
Remember to check that your schematic has no errors using the drc2 backend.
You can do it running 'gnetlist -g drc2 your_schematic.sch -o drc_output.txt'
and seeing the contents of the file drc_output.txt.
Loading schematic [/home/nano/TwoStageAmp/TwoStageAmp.sch]
WARNING: Symbol version mismatch on refdes Cout (capacitor-1.sym):
Symbol in library is newer than instantiated symbol
Minor version change (file 0.100, instantiated 0.000)
WARNING: Symbol version mismatch on refdes CE1 (capacitor-1.sym):
Symbol in library is newer than instantiated symbol
Minor version change (file 0.100, instantiated 0.000)
WARNING: Symbol version mismatch on refdes C1 (capacitor-1.sym):
Symbol in library is newer than instantiated symbol
Minor version change (file 0.100, instantiated 0.000)
WARNING: Symbol version mismatch on refdes CE2 (capacitor-1.sym):
Symbol in library is newer than instantiated symbol
Minor version change (file 0.100, instantiated 0.000)
WARNING: Symbol version mismatch on refdes C2 (capacitor-1.sym):
Symbol in library is newer than instantiated symbol
Minor version change (file 0.100, instantiated 0.000)
------------------------------------------------------
Verbose mode legend
n : Found net
C : Found component (staring to traverse component)
p : Found pin (starting to traverse pin / or examining pin)
P : Found end pin connection (end of this net)
R : Starting to rename a net
v : Found source attribute, traversing down
^ : Finished underlying source, going back up
u : Found a refdes which needs to be demangle
U : Found a connected_to refdes which needs to be demangle
------------------------------------------------------
- Starting internal netlist creation
CpnPnPpnPnnPpnnPnPPn CpnPnpnnP CpnPpnnPnPPn CpnnPnPPnpnP CpnPnnPpnP
CpnPpnnPP CpnnP
pnP CpnnPPpnnP CpnPpnnnPP CpnP CpnP CpnP CpnP CpnnPpnP CpnPpnP CpnP
CpnP CpnP CpnP C C C C Cpn
PnpnPnPnPn CpnnPPpnPnnPpnnPPnPn CpnP CpnP CpnPpnPnP CpnPnnPpnP CpnP
CpnPpnnnPP CpnP Cp
nPnpnnPP CpnPpnnPnPPn CpnnPPnPnpnP CpnP CpnP CpnPnpnPnPnPn DONE
- Staring post processing
- Naming nets:
pnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnp
npnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpnpn DONE
- Renaming nets:
DONE
- Resolving hierarchy:
DONE
DONE
- Staring post processing
- Naming nets of graphical objects:
DONE
Internal netlist representation:
component Q1
pin 3 () Vcoll1
Q1 3 [5]
RC1 1 [11464]
R8 1 [12491]
pin 1 () Vem1
Q1 1 [67]
RE1 2 [1753]
CE1 2 [2663]
pin 2 () Vbase1
Q1 2 [88]
R1 1 [1343]
R2 2 [1566]
C1 2 [9242]
component R5
pin 2 (2) 1
R5 2 [1121]
C1 1 [9233]
pin 1 (1) Vin
R5 1 [1130]
Vinput 1 [3051]
component R1
pin 2 (2) Vcc
R1 2 [1334]
pin 1 (1) Vbase1
R1 1 [1343]
Q1 2 [88]
R2 2 [1566]
C1 2 [9242]
component R2
pin 2 (2) Vbase1
R2 2 [1566]
Q1 2 [88]
R1 1 [1343]
C1 2 [9242]
pin 1 (1) GND
R2 1 [1575]
component RE1
pin 2 (2) Vem1
RE1 2 [1753]
Q1 1 [67]
CE1 2 [2663]
pin 1 (1) GND
RE1 1 [1762]
component RC2
pin 2 (2) Vcc
RC2 2 [1967]
pin 1 (1) VColl2
RC2 1 [1976]
Cout 1 [2369]
Q2 3 [9464]
component RL
pin 2 (2) Vout
RL 2 [2168]
Cout 2 [2378]
pin 1 (1) GND
RL 1 [2177]
component Cout
pin 1 (1) VColl2
Cout 1 [2369]
Q2 3 [9464]
RC2 1 [1976]
pin 2 (2) Vout
Cout 2 [2378]
RL 2 [2168]
component CE1
pin 1 (1) GND
CE1 1 [2654]
pin 2 (2) Vem1
CE1 2 [2663]
Q1 1 [67]
RE1 2 [1753]
component SPECIAL
pin 1 (1) Null net name
R2 1 [1575]
component SPECIAL
pin 1 (1) Null net name
RE1 1 [1762]
component SPECIAL
pin 1 (1) Null net name
CE1 1 [2654]
component SPECIAL
pin 1 (1) Null net name
RL 1 [2177]
component Vinput
pin 1 (+) Vin
Vinput 1 [3051]
R5 1 [1130]
pin 2 (-) GND
Vinput 2 [3067]
component VCC
pin 1 (+) Vcc
VCC 1 [3890]
pin 2 (-) GND
VCC 2 [3909]
component SPECIAL
pin 1 (1) Null net name
VCC 1 [3890]
component SPECIAL
pin 1 (1) Null net name
RC2 2 [1967]
component SPECIAL
pin 1 (1) Null net name
VCC 2 [3909]
component SPECIAL
pin 1 (1) Null net name
Vinput 2 [3067]
component A1
component A2
component A3
component C1
pin 1 (1) 1
C1 1 [9233]
R5 2 [1121]
pin 2 (2) Vbase1
C1 2 [9242]
Q1 2 [88]
R1 1 [1343]
R2 2 [1566]
component Q2
pin 3 () VColl2
Q2 3 [9464]
Cout 1 [2369]
RC2 1 [1976]
pin 1 () Vem2
Q2 1 [9499]
RE2 2 [11702]
CE2 2 [12127]
pin 2 () Vbase2
Q2 2 [9516]
R4 2 [13072]
C2 2 [13413]
R3 1 [12848]
component SPECIAL
pin 1 (1) Null net name
RE2 1 [11711]
component SPECIAL
pin 1 (1) Null net name
R1 2 [1334]
component RC1
pin 2 (2) Vcc
RC1 2 [11455]
pin 1 (1) Vcoll1
RC1 1 [11464]
Q1 3 [5]
R8 1 [12491]
component RE2
pin 2 (2) Vem2
RE2 2 [11702]
Q2 1 [9499]
CE2 2 [12127]
pin 1 (1) GND
RE2 1 [11711]
component SPECIAL
pin 1 (1) Null net name
RC1 2 [11455]
component CE2
pin 1 (1) GND
CE2 1 [12118]
pin 2 (2) Vem2
CE2 2 [12127]
Q2 1 [9499]
RE2 2 [11702]
component SPECIAL
pin 1 (1) Null net name
CE2 1 [12118]
component R8
pin 2 (2) 2
R8 2 [12482]
C2 1 [13404]
pin 1 (1) Vcoll1
R8 1 [12491]
Q1 3 [5]
RC1 1 [11464]
component R3
pin 2 (2) Vcc
R3 2 [12839]
pin 1 (1) Vbase2
R3 1 [12848]
Q2 2 [9516]
R4 2 [13072]
C2 2 [13413]
component R4
pin 2 (2) Vbase2
R4 2 [13072]
Q2 2 [9516]
C2 2 [13413]
R3 1 [12848]
pin 1 (1) GND
R4 1 [13081]
component SPECIAL
pin 1 (1) Null net name
R4 1 [13081]
component SPECIAL
pin 1 (1) Null net name
R3 2 [12839]
component C2
pin 1 (1) 2
C2 1 [13404]
R8 2 [12482]
pin 2 (2) Vbase2
C2 2 [13413]
Q2 2 [9516]
R4 2 [13072]
R3 1 [12848]
Probably parenthesis mismatch in /usr/share/gEDA/scheme/gnet-spice-sdb.scm
Most recently read form: (#@begin #<unspecified>)
ERROR: Unbound variable: spice-sdb
$rpm -qa | grep guile
guile-devel-1.8.0-8.20060831cvs
guile-1.8.0-8.20060831cvs
could you tell me what you think might be the problem? ill ask the
fedora team to make the changes.
nano
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