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Re: gEDA-user: Request for VHDL and Hierarchical Spice References
Since I build a "flat" netlist for each sheet it should be fairly
streight forward to build a hierarchical netlist thus I think it will
just be a syntax issue for the various formats.
As a side note: I have moved the reading of schematics from the c code
to a guile script. I am in process of doing the same for symbols and
plan to also write the schematics, symbol files with guile scripts.
The netlist application will allow the user to select which script they
want for reading and writting thus it should support both standard gda
and my non-stock, (tm) Peter C, file formats. Theoretically, given a
file structure one should be able to write scripts for any schematic
capture program and then this could function as a translator as well.
I have been putting together a more extensive and documented guile api
to interact with the library contanded data structures.
All of this together with a functioning hierarchical bus support and the
addition of hierarchical netlists should as I claimed earlier be
interesting.
Thanks David, Dan and Al for the pointers to the netlist formats.
Steve Meier
On Wed, 2007-11-28 at 12:54 -0500, Dan McMahill wrote:
> Steve Meier wrote:
> > I am seeking good references for verilog, VHDL and spice syntext
> > specificaly with the idea of supporting hierarchical net lists. Online
> > or recomendations for purchase.
> >
> > I desire this material as my code is reaching a level of maturity that
> > would make simulation of complex designs interesting.
> >
> > Thanks,
> >
> > Steve Meier
>
> For verilog and "spice" (I'm including things like spice2, spice3,
> hspice, spectre, etc under the "spice" heading), it is quite simple.
>
> note, exact syntax may vary for the passing of parameters, but this
> should demonstrate the idea. See
> http://www.ece.uci.edu/docs/hspice/hspice_2001_2-43.html for examples of
> hspice.
>
> You'll note that there is almost nothing special or extra to do with
> hierarchy. You simply have a flat netlist for each level in the
> hierarchy and instantiate subcircuits.
>
> --- SPICE ------------------------------------------------------
>
> * basic CMOS inverter with parameter passing (in, out, vdd, vss)
> .subckt myinv 1 2 100 200 WP=30u WN=10u
> M1 2 1 100 100 PFET W='WP' L=1u
> M2 2 1 200 200 NFET W='WN' L=1u
> .ends
>
> * a buffer (non inverting)
> .subckt mybuf in out vdd vss N=1
> xinv1 in inv vdd vss myinv WP='N*10u' WN='N*5u'
> xinv2 inv out vdd vss myinv WP='N*30u' WN='N*15u'
> .ends
>
> * and now a circuit which uses the buffer
>
> * power/ground
> vvdd vdd 0 dc 5.0
> vvss vss 0 dc 0.0
>
> * a 1x buffer
> xbuf1 in buf1_out vdd vss mybuf
>
> * a 4x buffer
> xbuf2 in buf2_out vdd vss mybuf N=4
>
> * add stimulus, etc here...
>
> --- SPICE ------------------------------------------------------
>
> --- spectre ------------------------------------------------------
>
> // basic CMOS inverter with parameter passing (in, out, vdd, vss)
> subckt myinv 1 2 100 200
> parameters WP=30u WN=10u
> M1 (2 1 100 100) PFET W=WP L=1u
> M2 (2 1 200 200) NFET W=WN L=1u
> ends myinv
>
> // a buffer (non inverting)
> subckt mybuf in out vdd vss
> parameters N=1
> xinv1 (in inv vdd vss) myinv WP=N*10u WN=N*5u
> xinv2 (inv out vdd vss) myinv WP=N*30u WN=N*15u
> ends mybuf
>
> // and now a circuit which uses the buffer
>
> // power/ground
> vvdd (vdd 0) vsource type=dc dc=5.0
> vvss (vss 0) vsource type=dc dc=0.0
>
> // a 1x buffer
> xbuf1 (in buf1_out vdd vss) mybuf
>
> // a 4x buffer
> xbuf2 (in buf2_out vdd vss) mybuf N=4
>
> // add stimulus, etc here...
>
> --- spectre ------------------------------------------------------
>
> --- verilog ------------------------------------------------------
>
> module myinv(in out vdd vss)
> input in, vdd, vss;
> output out;
> wire out;
>
> parameter DELAY=5;
>
> // (I may have the delay syntax wrong, verilog book isn't in front of me)
> assign #DELAY out = ~in;
> endmodule
>
> module mybuf(in out vdd vss)
> input in, vdd, vss;
> output out;
> wire int, out;
>
> defparam inv1.DELAY=2
> myinv inv1(.in(in), .out(int), .vdd(vdd), .vss(vss))
> defparam inv1.DELAY=3
> myinv inv2(.in(int),.out(out), .vdd(vdd), .vss(vss))
>
> endmodule
>
> module testbench
>
> wire in, out1, out2;
> reg vdd, vss;
>
> mybuf buf1(.in(in), .out(out1), .vdd(vdd), .vss(vss))
> mybuf buf2(.in(in), .out(out2), .vdd(vdd), .vss(vss))
>
> // some stimulus here...
> endmodule
>
> --- verilog ------------------------------------------------------
>
>
>
> In all of these, the basic idea is the same. Each level of hierarchy
> has its own netlist inside of a subcircuit or a module. Then other
> blocks are instantiated.
>
> Note the decided lack of doing anything silly like producing a flattened
> netlist for the whole design. That kills the ability for humans to
> effectively read the netlist (needed all too often) and simulators to do
> various optimizations.
>
> Hope this helps.
>
> -Dan
>
>
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