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gEDA-user: Request for VHDL and Hierarchical Spice References

I am seeking good references for verilog, VHDL and spice syntext
specificaly with the idea of supporting hierarchical net lists. Online
or recomendations for purchase.

I desire this material as my code is reaching a level of maturity that
would make simulation of complex designs interesting.

Thanks,

Steve Meier



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