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Re: gEDA-user: New autorouter high effort mode

   > Date: Thu, 25 Nov 2010 21:39:28 +1100
   > From: silicon.on.inspiration@xxxxxxxxx
   > To: geda-user@xxxxxxxxxxxxxx
   > Subject: Re: gEDA-user: New autorouter high effort mode
   >
   > >
   > > Yes, I'm working on a fix for these problems.
   >
   > These problems are now solved with my most recent git push.
   > It also now updates the display every time a better result is found,
   > so you can see what's going on more clearly.
   I'm waiting to see some screencasts (resistor pr0n again) how this is
   working but I was wondering is it possible to run HE autorouter to
   optimize vias?
   This might be good solution for getting smaller PCBs. Usually I make my
   first prototype with huge board and a lot of testpoints after verifying
   it I start to make smaller.
   I'm still running stable version since I fear to break my design
   process with devel versions so I'm just curious.
   Hannu Vuolasaho


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