gEDA-user: Buses in gEDA/gaf

[msokolov@xxxxxxxxxxxxxxx (Michael Sokolov)]

Hello again fellow gEDA users,

As my OSDCU design is a microprocessor system of moderate complexity, I
need to use buses on my schematics -- for my microprocessor's address
and data buses and everything connected to them.  I haven't been able to
find any real documentation on buses in gEDA/gaf (all documentation says
they are a brand new feature, yet right now I'm using version 20040111,
more than 2 y old, which has them -- can't be *that* new...), so I have
a few questions for the list:

1. There doesn't seem to be any way to indicate how wide a bus is in
   bits, i.e., how many nets should it turn into.  Does gEDA not care?
   How can it not care?  How many nets is the netlister going to
   generate for a bus?

2. How do I label my buses, i.e., what's the bus equivalent of the
   netname= attribute?  Is it busname=?  It isn't in the master
   attribute list.

3. When I connect a net to a bus, the bus ripper symbol appears.  But
   how do I tell it which bit of the bus to connect to?  I.e., what
   would keep the netlister from mixing up the bits of the address and
   data buses?  Is it just the netname= attributes on the individual
   nets before they connect to the bus?  In other words, are buses
   really just graphics ignored by the netlister?

4. I need to carry my address and data buses across multiple pages of a
   (non-hierarchical) multipage schematics, i.e., I need to create bus
   connector symbols for schematic page cross-reference.  Is it
   possible?  Would it involve drawing a connector symbol with a bus pin
   instead of the regular pin type?  I see support for that in the file
   format document, but does it actually work?

TIA for any answers,

MS


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