Re: gEDA-user: gPCB Polygon Best Practices

[DJ Delorie <dj@xxxxxxxxxxx>]

> If I can get away with 2 layers I want a GND plane on the bottom
> layer which will be split up by traces that just couldn't fit on the
> components side of the board.

I did something like that here: http://www.delorie.com/pcb/m3a/

> 1. Even after the polygon was cleared from the trace the rat's nest
> was claiming that the net associated with the trace on solder side was
> shorting with GND???  I remove the trace and the error goes away...if
> I leave the trace and remvoe the GND plane the error goes away.  How
> do I figure out what is wrong when visually the GND polygon is
> clearing the net?

You might have a "stub" trace under one of the pads.  Try disabling
the pin and via layers to see if there's a tiny trace under one of
them.

> 2. Should I draw the GND plane at the beginning or should it be the
>    last step?

What I did was run traces for power and ground, and complete and DRC
the design that way, including checking for shorts.  Then, I added
the polygons one at a time, re-testing after each.

> 3. I have unplated holes on one of my symbols that is enforcing a
> clearance on the component side but not on the Solder side.  After I
> drew polygon associated with GND_SLDER I get warnings about a
> polygon to close to the holes.  Why is there not a clearance on the
> Solder side of the board enforced for nonplated holes?  How do I get
> this clearance around the holes to work?

Might be easier and cheaper to make it a plated hole; most fabs charge
extra for nonplated holes.  But, it should work anyway.  Can you come
up with a minimum example board that demonstrates this?

> 4. Layer assignments.  I understand that PCB goes up to 8 layers.

16 layers.  8 is just the default starting set; you can add and remove
layers as your design needs.

You can go higher than 16 is you recompile; edit MAX_LAYER in
globalconst.h

> In the preferences there is up to 8 groups and 8 different buttons
> two of which are unassigned by default.  If I changed my design to a
> 4 layer design with the following configuration:
> 
> Bottom (Layer 4): Signal and components
> Middle (Layer 3): GND
> Middle (Layer 2): VCC: 3.3, 5, and 12
> Top (Layer 1): Signal and components
> 
> How would I configure the groups and Y axis buttons in PCB layer
> preferences to acheive the results above?  I saw in the info tab an
> example but I don't think it's exactly what I'm after.

For a four layer design, just assign the first four layers to the four
copper layers, and put each in their own group.  You can either delete
the remaining layers, or assign them to a separate group.  If you need
a board outline layer, assign that its own group also.

When I did my board, I assigned five layers to each side of the board,
only because I wanted different signals to be colored differently.  I
had colors for trace, power trace, power poly, ground trace, and
ground poly; for each side.  Ten layers for a two-layer board.  It
came in handy, as I could de-group the poly layers to hide them or
re-check the trace connectivity, or to show only the polygons when
editing them became tricky.


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