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Re: gEDA-user: gPCB Polygon Best Practices

DJ Delorie wrote:
If I can get away with 2 layers I want a GND plane on the bottom
layer which will be split up by traces that just couldn't fit on the
components side of the board.

I did something like that here: http://www.delorie.com/pcb/m3a/

1. Even after the polygon was cleared from the trace the rat's nest
was claiming that the net associated with the trace on solder side was
shorting with GND??? I remove the trace and the error goes away...if
I leave the trace and remvoe the GND plane the error goes away. How
do I figure out what is wrong when visually the GND polygon is
clearing the net?

You might have a "stub" trace under one of the pads.  Try disabling
the pin and via layers to see if there's a tiny trace under one of
them.

I took a look at this over my lunch break. You were right I had my grid setting to 10 mill and my 80 mill trace had a really short small line right before it connected to the via. The polygon wasn't visually touching the line but it was creating a point right at the short line. When I redrew the line with a larger grid and payed closer attention to making longer continuous lines I was able to <key> j on all the lines. After <key> o the route was complete and there were not shorts to that net. Thanks a lot for the tip. Tips like this really help cut down the learning curve.
2. Should I draw the GND plane at the beginning or should it be the
last step?

What I did was run traces for power and ground, and complete and DRC
the design that way, including checking for shorts.  Then, I added
the polygons one at a time, re-testing after each.

Ok
3. I have unplated holes on one of my symbols that is enforcing a
clearance on the component side but not on the Solder side. After I
drew polygon associated with GND_SLDER I get warnings about a
polygon to close to the holes. Why is there not a clearance on the
Solder side of the board enforced for nonplated holes? How do I get
this clearance around the holes to work?

Might be easier and cheaper to make it a plated hole; most fabs charge
extra for nonplated holes.  But, it should work anyway.  Can you come
up with a minimum example board that demonstrates this?

I plan on changing them to make it cheaper I just wanted to invest the time now in understanding what I'm doing wrong. I'll make a simple example and make a new post for this.
4. Layer assignments. I understand that PCB goes up to 8 layers.

16 layers.  8 is just the default starting set; you can add and remove
layers as your design needs.

You can go higher than 16 is you recompile; edit MAX_LAYER in
globalconst.h

In the preferences there is up to 8 groups and 8 different buttons
two of which are unassigned by default.  If I changed my design to a
4 layer design with the following configuration:

Bottom (Layer 4): Signal and components
Middle (Layer 3): GND
Middle (Layer 2): VCC: 3.3, 5, and 12
Top (Layer 1): Signal and components

How would I configure the groups and Y axis buttons in PCB layer
preferences to acheive the results above? I saw in the info tab an
example but I don't think it's exactly what I'm after.

For a four layer design, just assign the first four layers to the four
copper layers, and put each in their own group.  You can either delete
the remaining layers, or assign them to a separate group.  If you need
a board outline layer, assign that its own group also.

When I did my board, I assigned five layers to each side of the board,
only because I wanted different signals to be colored differently.  I
had colors for trace, power trace, power poly, ground trace, and
ground poly; for each side.  Ten layers for a two-layer board.  It
came in handy, as I could de-group the poly layers to hide them or
re-check the trace connectivity, or to show only the polygons when
editing them became tricky.


So if I'm understanding this correctly let me re-summarize, inserting a few more questions as we go. The actual number of manufactured layers is determined by the number of groups in use. The buttons labeled "layers" in PCB is actually associated copper. PCB allows you to have a number of different "sets of associated copper"(PCB layers) to be on the same manufactured layer. Each group of copper be assigned different colors to help visualize the purpose of each set.

How do you communicate to the board house which group(manufactured layer) is the top or layer 1(top), 2,3, bottom? Perhaps it's not so much that there is a top an bottom as it is which copper is grouped with each other.

Is their a way to assign a "PCB layer" or set of copper to a specific net? So for instance my GND plane or polygon would be assigned to the GND net. Then each pad or pin that needs to be connected to the GND net would actual draw a rat to my GND plane helping me to visualize the routes that actually cross. 
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