Re: gEDA-user: pcb prevents overlapping vias

[kai-martin knaak <kmk@xxxxxxxxxxxxxxx>]

Ineiev wrote:

>> The trigger for refusal seems to be overlapping annulus.
> 
> Reported three years ago:
> 
http://sourceforge.net/tracker/?func=detail&aid=1687692&group_id=73743&atid=538811

Yes, this seems to be the same non-feature. 


> The cited report said such vias were removed on subsequent file load.
> aren't they now?

My footprint loads fine. 
However, I can still reproduce the 2007 case, which is raw vias
and lines. Via no. 14 is silently dropped. Seems like pcb only second 
guesses vias but not pins. 

---<)kaimartin(>---
-- 
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53



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