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gEDA-user: Verilog netlist problems
People,
I have created a gEDA schematic comprised of 4 Verilog submodules, each
having its own (hand generated) netlist, along with the attendant IPAD's
and OPAD's. Each submodule has passed verilog testing using it's own
testfixture file.
I generated a netlist for the schematic using the gEDA command:
gnetlist -g verilog -o APSChip.v APSChip-2.sch
Said netlist (APSChip.v) file is attached below. From anything I can
see, it seems to have generated just fine, yet when I attempt to perform
a verilog compilation, I get a 2 errors (vlogTST.sav) that I simply
don't understand. I am attaching the following files:
RCVALG.v
RCVCNTRL.v
RCVDLYCNTRL.v
RCVPLSTMR.v
vlogTST.sav
APSChip.v
testfixture.v
I would appreciate your reviewing this information and suggesting just
what it is that I'm doing wrong.
Harold Skank
/* Author.......H. Skank */
`timescale 10ns / 10ps
module RCVALG(
Hit,
Strt,
DtaIn,
Clk,
);
/* Port directions begin here */
output reg Hit;
input Strt;
input DtaIn;
input Clk;
/* Declare needed variables */
reg [39:0] DtaRcd;
reg [39:0] corr;
reg [39:0] CorrFrame = 40'h 0f0f0f0f0f;
reg [1:0] Asum [19:0];
reg [2:0] Bsum [9:0];
reg [3:0] Csum [4:0];
reg [4:0] Dsum [1:0];
reg [5:0] Temp;
reg [7:0] AveA1, AveA0;
reg [5:0] Word[4:0];
reg [7:0] CntOt;
always @ (posedge Clk) begin
if (Strt == 1) begin
Hit = 0;
DtaRcd = DtaRcd >> 1;
DtaRcd[39] = DtaIn;
corr = DtaRcd ~^ CorrFrame;
Asum[19] = corr[39] + corr[38];
Asum[18] = corr[37] + corr[36];
Asum[17] = corr[35] + corr[34];
Asum[16] = corr[33] + corr[32];
Asum[15] = corr[31] + corr[30];
Asum[14] = corr[29] + corr[28];
Asum[13] = corr[27] + corr[26];
Asum[12] = corr[25] + corr[24];
Asum[11] = corr[23] + corr[22];
Asum[10] = corr[21] + corr[20];
Asum[9] = corr[19] + corr[18];
Asum[8] = corr[27] + corr[16];
Asum[7] = corr[15] + corr[14];
Asum[6] = corr[13] + corr[12];
Asum[5] = corr[11] + corr[10];
Asum[4] = corr[9] + corr[8];
Asum[3] = corr[7] + corr[6];
Asum[2] = corr[5] + corr[4];
Asum[1] = corr[3] + corr[2];
Asum[0] = corr[1] + corr[0];
Bsum[9] = Asum[19] + Asum[18];
Bsum[8] = Asum[17] + Asum[16];
Bsum[7] = Asum[15] + Asum[14];
Bsum[6] = Asum[13] + Asum[12];
Bsum[5] = Asum[11] + Asum[10];
Bsum[4] = Asum[9] + Asum[8];
Bsum[3] = Asum[7] + Asum[6];
Bsum[2] = Asum[5] + Asum[4];
Bsum[1] = Asum[3] + Asum[2];
Bsum[0] = Asum[1] + Asum[0];
Csum[4] = Bsum[9] + Bsum[8];
Csum[3] = Bsum[7] + Bsum[6];
Csum[2] = Bsum[5] + Bsum[4];
Csum[1] = Bsum[3] + Bsum[2];
Csum[0] = Bsum[1] + Bsum[0];
Dsum[1] = Csum[4] + Csum[3];
Dsum[0] = Csum[2] + Csum[1];
Temp = Dsum[1] + Dsum[0] + Csum[0];
Word[0] = Word[1]; // Do a right shift
Word[1] = Word[2];
Word[2] = Word[3];
Word[3] = Word[4];
Word[4] = Temp; // Shift in new info
AveA1 = Word[4] + Word[3];
AveA0 = Word[1] + Word[0];
CntOt = Word[2] + AveA1 + AveA0;
if (CntOt > 135) Hit = 1;
end
end
endmodule // RCVALG.v
/* Author: H. Skank */
`timescale 10ns / 10 ps // timescale directive
`define Gain0 10001000 // Minimum Gain Configuration
`define Gain1 01001000
`define Gain2 00101000
`define Gain3 00011000
`define Gain4 00010100
`define Gain5 00010010
`define Gain6 00010001 // Maximum Gain Configuration
module RCVCNTRL(
StrtAlg,
Gain[7:0],
TrnsfrMsg,
RcvMsg[11:0],
StrtTmr,
StrtDly,
AlgClk,
CyclDn,
DlyDn,
Hit,
BfrMt,
TrnsfrDn,
ClkX64
);
/* Port directions begin here */
output reg StrtAlg; // Start algorithm flag
output reg [7:0] Gain; // AGC Port Output
output reg TrnsfrMsg; // Transfer message flag
output reg [11:0] RcvMsg; // Receive message
output reg StrtTmr; // Start flag
output reg StrtDly; // Start recovery delay flag
output reg AlgClk; // Clock for Algorithm Circuit
input CyclDn; // Transmit timing cycle done flag
input DlyDn; // Recovdry delay done flag
input Hit; // Message detect bit
input BfrMt; // RS-232 Buffer Empty flag
input TrnsfrDn; // Transfer completion flag
input ClkX64; // Transmit timing clock
/* Declare necessary internal variables */
reg [4:0] State;
reg AlgClkCnt;
always @ (negedge ClkX64) begin
if (StrtAlg == 0) StrtAlg = 1;
AlgClkCnt = AlgClkCnt + 1;
if (AlgClkCnt == 4) AlgClk = 0;
if (AlgClkCnt == 8) begin
AlgClkCnt = 0;
AlgClk = 1;
end
case (State)
5'd 0: begin // State-0, Idle State
Gain = `Gain6; // Set Maximum Gain
StrtAlg = 1; // Start the receive algorithm
if (Hit) begin
RcvMsg[0] = 1; // Set Start-bit
StrtTmr = 1; // Start Pulse Timer
State = 1; // To State-1
end
end
5'd 1: begin
if (CyclDn) begin // State-1, Wait for delay
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 3; // To State-2
end
end
5'd 3: begin
if (DlyDn) begin // State-2, Recovery delay done
if (Hit) RcvMsg[1] = 1; // Set Bit-1
else RcvMsg[1] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 2; // To State-3
end
end
5'd 2: begin // State-3, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 6; // To State-4
end
end
5'd 6: begin // State-4, Recovery delay done
if (DlyDn) begin
if (Hit) RcvMsg[2] = 1; // Set Bit-2
else RcvMsg[2] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 7; // To State-5
end
end
5'd 7: begin // State-5, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 5; // To State-6
end
end
5'd 5: begin // State-6, Recovery delay done
if (DlyDn) begin
if (Hit) RcvMsg[3] = 1; // Set Bit-3
else RcvMsg[3] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 4; // To State-7
end
end
5'd 4: begin // State-7, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 12; // To State-8
end
end
5'd 12: begin // State-8, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[4] = 1; // Set Bit-4
else RcvMsg[4] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 13; // To State-9
end
end
5'd 13: begin // State-9, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 15; // To State-10
end
end
5'd 15: begin // State-10, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[5] = 1; // Set Bit-5
else RcvMsg[5] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 14; // To State-11
end
end
5'd 14: begin // State-11, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 10; // To State-12
end
end
5'd 10: begin // State-12, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[6] = 1; // Set Bit-6
else RcvMsg[6] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 26; // To State-13
end
end
5'd 26: begin // State-13, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 30; // To State-14
end
end
5'd 30: begin // State-14, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[7] = 1; // Set Bit-7
else RcvMsg[7] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 31; // To State-15
end
end
5'd 31: begin // State-15, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 29; // To State-16
end
end
5'd 29: begin // State-16, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[8] = 1; // Set Bit-8
else RcvMsg[8] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 28; // To State-17
end
end
5'd 28: begin // State-17, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 20; // To State-18
end
end
5'd 20: begin // State-18, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[9] = 1; // Set Bit-9
else RcvMsg[9] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 21; // To State-19
end
end
5'd 21: begin // State-19, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 23; // To State-20
end
end
5'd 23: begin // State-20, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[10] = 1; // Set Bit-10
else RcvMsg[10] = 0;
StrtDly = 0;
StrtTmr = 1;
State = 22; // To State-21
end
end
5'd 22: begin // State-21, Wait for delay
if (CyclDn) begin
StrtTmr = 0; // Stop Pulse Timer
StrtDly = 1; // Start Delay Timer
State = 18; // To State-22
end
end
5'd 18: begin // State-22, Wait for recover
if (DlyDn) begin
if (Hit) RcvMsg[11] = 1; // Set Stop-bit
else RcvMsg[10] = 1; // Otherwise, force Stop-bit
StrtDly = 0;
State = 19; // To State-23
end
end
5'd 19: begin // State-23, Transfer message
if (BfrMt) begin
TrnsfrMsg = 1;
State = 17; // To State-24
end
end
5'd 17: begin // State-24, Wait for recover
if (TrnsfrDn) begin
TrnsfrMsg = 0;
State = 0; // To State-0
end
end
endcase
end
endmodule // RCVCNTRL
/* Author: H. Skank */
`timescale 10ns / 10 ps // timescale directive
module RCVDLYCNTRL(
DlyDn,
Strt,
ClkX64,
);
/* Port directions begin here */
output reg DlyDn;
input Strt;
input ClkX64;
/* Declare necessary internal variables */
reg [11:0] State;
reg Run,Cycle;
always @ (posedge ClkX64) begin
if (Strt) Run = 1;
else if (~Strt) Run = 0;
if ((Run == 1) & (Cycle == 0)) Cycle = 1;
if (Cycle == 1) begin
State = State + 1;
if (State == 3000) DlyDn = 1;
else if (State == 3001) begin
DlyDn = 0;
State = 0;
Cycle = 0;
end
end
else DlyDn = 0;
end
endmodule // RCVDLYCNTRL
/* Author: H. Skank */
`timescale 10ns / 10 ps // timescale directive
module RCVPLSTMR(
CyclDn,
Strt,
ClkX64,
);
/* Port directions begin here */
output reg CyclDn;
input Strt;
input ClkX64;
/* Declare necessary internal variables */
reg [8:0] Count;
reg cycle; // 1 => cycle running
always @ (posedge ClkX64) begin
if (Strt) begin
cycle = 1;
Count = 0;
end
if (cycle == 1) begin
Count = Count + 1;
if (Count == 321) begin
Count = 0;
CyclDn = 1;
cycle = 0;
end
else CyclDn = 0;
end
end
endmodule // RCVCNTRLB
[designer@AMD APSChip]$ ./vlogTST
/home/designer/Etrema/APSChip/APSChip.v:49: error: port ``RcvMsg'' is not a port of U23.
/home/designer/Etrema/APSChip/APSChip.v:49: error: port ``Gain'' is not a port of U23.
2 error(s) during elaboration.
[designer@AMD APSChip]$
/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
/* Id ..........$Id: gnet-verilog.scm,v 1.14 2005/02/03 12:49:36 danmc Exp $ */
/* Source.......$Source: /home/cvspsrv/cvsroot/eda/geda/devel/gnetlist/scheme/gnet-verilog.scm,v $ */
/* Revision.....$Revision: 1.14 $ */
/* Author.......$Author: danmc $ */
module APSChip (
TrnsfrDn ,
BfrMt ,
ClkX64 ,
DtaIn ,
RcvMsg ,
TrnsfrMsg ,
Gain
);
/* Port directions begin here */
input TrnsfrDn ;
input BfrMt ;
input ClkX64 ;
input DtaIn ;
output [ 11 : 0 ] RcvMsg ;
output TrnsfrMsg ;
output [ 7 : 0 ] Gain ;
/* Wires from the design */
wire [ 11 : 0 ] RcvMsg ;
wire TrnsfrMsg ;
wire TrnsfrDn ;
wire BfrMt ;
wire [ 7 : 0 ] Gain ;
wire DtaIn ;
wire unnamed_net7 ;
wire unnamed_net6 ;
wire unnamed_net5 ;
wire unnamed_net4 ;
wire unnamed_net3 ;
wire unnamed_net2 ;
wire ClkX64 ;
wire unnamed_net1 ;
/* continuous assignments */
/* Package instantiations */
RCVCNTRL U23 (
.Hit ( unnamed_net7 ),
.TrnsfrMsg ( TrnsfrMsg ),
.RcvMsg ( RcvMsg[11:0] ),
.StrtTmr ( unnamed_net3 ),
.BfrMt ( BfrMt ),
.DlyDn ( unnamed_net2 ),
.ClkX64 ( ClkX64 ),
.TrnsfrDn ( TrnsfrDn ),
.Gain ( Gain[7:0] ),
.CyclDn ( unnamed_net4 ),
.StrtDly ( unnamed_net1 ),
.StrtAlg ( unnamed_net5 ),
.AlgClk ( unnamed_net6 )
);
RCVALG U22 (
.Strt ( unnamed_net5 ),
.Clk ( unnamed_net6 ),
.Hit ( unnamed_net7 ),
.DtaIn ( DtaIn )
);
RCVPLSTMR U21 (
.Strt ( unnamed_net3 ),
.ClkX64 ( ClkX64 ),
.CyclDn ( unnamed_net4 )
);
RCVDLYCNTRL U20 (
.Strt ( unnamed_net1 ),
.ClkX64 ( ClkX64 ),
.DlyDn ( unnamed_net2 )
);
endmodule
/*
* This is a testfixture file intended to call a module for
* initial testing.
*/
`timescale 10ns / 10ps // timescale directive
module testfixture;
wire [7:0] Gain; // list the dut variables
wire TrnsfrMsg;
wire [11:0] RcvMsg;
reg DtaIn;
reg ClkX64;
reg [8:0] CntOt; // list the necessary program variables
reg [7:0] index;
reg [39:0] DtaRcd;
wire [39:0] corr;
APSChip dut (.Gain(Gain[7:0]), .TrnsfrMsg(TrnsfrMsg), .RcvMsg(RcvMsg[11:0]),.DtaIn(DtaIn), .BfrMt(BfrMt) ,.TrnsfrDn(TrnsfrDn), .ClkX64(ClkX64));
initial begin
$monitor($time,,"StrtAlg=%b index=%d ClkX64=%b DtaIn=%b DtaRcd=%b corr=%b Temp=%d CntOt=%d Hit=%b",
dut.U23.StrtAlg, index, ClkX64, DtaIn, dut.U22.DtaRcd, dut.U22.corr, dut.U22.Temp, dut.U22.CntOt, dut.U22.Hit);
begin
ClkX64 = 0;
DtaIn = 0;
index = 0;
dut.U23.StrtAlg = 0;
force dut.U22.DtaRcd = 40'h 0;
end
@ (negedge ClkX64); // wait for a cycle
release dut.U22.DtaRcd;
@ (negedge ClkX64) DtaIn = 0;
@ (negedge ClkX64);
@ (negedge ClkX64);
@ (negedge ClkX64) dut.U23.StrtAlg = 1;
for (index = 0; index < 120; index = index + 1) begin
@ (negedge dut.U22.Clk) begin
case (index)
0: DtaIn = 1;
1: DtaIn = 0;
2: DtaIn = 1;
3: DtaIn = 0;
4: DtaIn = 1;
5: DtaIn = 0;
6: DtaIn = 1;
7: DtaIn = 0;
8: DtaIn = 1;
9: DtaIn = 0;
10: DtaIn = 1;
11: DtaIn = 0;
12: DtaIn = 1;
13: DtaIn = 0;
14: DtaIn = 1;
15: DtaIn = 0;
16: DtaIn = 1;
17: DtaIn = 0;
18: DtaIn = 1;
19: DtaIn = 0;
20: DtaIn = 1;
21: DtaIn = 0;
22: DtaIn = 1;
23: DtaIn = 0;
24: DtaIn = 1;
25: DtaIn = 0;
26: DtaIn = 1;
27: DtaIn = 0;
28: DtaIn = 1;
29: DtaIn = 0;
30: DtaIn = 1;
31: DtaIn = 0;
32: DtaIn = 1;
33: DtaIn = 0;
34: DtaIn = 1;
35: DtaIn = 0;
36: DtaIn = 1;
37: DtaIn = 0;
38: DtaIn = 1;
39: DtaIn = 0;
40: DtaIn = 1;
41: DtaIn = 1;
42: DtaIn = 1;
43: DtaIn = 1;
44: DtaIn = 0;
45: DtaIn = 0;
46: DtaIn = 0;
47: DtaIn = 0;
48: DtaIn = 1;
49: DtaIn = 1;
50: DtaIn = 1;
51: DtaIn = 1;
52: DtaIn = 0;
53: DtaIn = 0;
54: DtaIn = 0;
55: DtaIn = 0;
56: DtaIn = 1;
57: DtaIn = 1;
58: DtaIn = 1;
59: DtaIn = 1;
60: DtaIn = 0;
61: DtaIn = 0;
62: DtaIn = 0;
63: DtaIn = 0;
64: DtaIn = 1;
65: DtaIn = 1;
66: DtaIn = 1;
67: DtaIn = 1;
68: DtaIn = 0;
69: DtaIn = 0;
70: DtaIn = 0;
71: DtaIn = 0;
72: DtaIn = 1;
73: DtaIn = 1;
74: DtaIn = 1;
75: DtaIn = 1;
76: DtaIn = 0;
77: DtaIn = 0;
78: DtaIn = 0;
79: DtaIn = 0;
80: DtaIn = 1;
81: DtaIn = 0;
82: DtaIn = 1;
83: DtaIn = 0;
84: DtaIn = 1;
85: DtaIn = 0;
86: DtaIn = 1;
87: DtaIn = 0;
88: DtaIn = 1;
89: DtaIn = 0;
90: DtaIn = 1;
91: DtaIn = 0;
92: DtaIn = 1;
93: DtaIn = 0;
94: DtaIn = 1;
95: DtaIn = 0;
96: DtaIn = 1;
97: DtaIn = 0;
98: DtaIn = 1;
99: DtaIn = 0;
100: DtaIn = 1;
101: DtaIn = 0;
102: DtaIn = 1;
103: DtaIn = 0;
104: DtaIn = 1;
105: DtaIn = 0;
106: DtaIn = 1;
107: DtaIn = 0;
108: DtaIn = 1;
109: DtaIn = 0;
110: DtaIn = 1;
111: DtaIn = 0;
112: DtaIn = 1;
113: DtaIn = 0;
114: DtaIn = 1;
115: DtaIn = 0;
116: DtaIn = 1;
117: DtaIn = 0;
118: DtaIn = 1;
119: DtaIn = 0;
endcase
end
end
end
always begin
ClkX64 = !ClkX64;
if (index == 120) $finish;
end
endmodule // testfixture.v