Re: gEDA-user: Verilog netlist problems

[Mike Jarabek <mjarabek@xxxxxxxxx>]

Hi,

    I don't think you want to have things like Gain[7:0] and RcvMsg[11:0]
in your module declaration:

module RCVCNTRL(
	StrtAlg,
	Gain[7:0],
	TrnsfrMsg,
	RcvMsg[11:0],
	StrtTmr,
	StrtDly,
	AlgClk,
	CyclDn,
	DlyDn,
	Hit,
	BfrMt,
	TrnsfrDn,
	ClkX64
         );

Modelsim's error is (only) slightly more informative than Icarus':
------------
[mjarabek@scotty verilog]$ vlog -work work *.v
Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
-- Compiling module APSChip
-- Compiling module RCVALG
-- Compiling module RCVCNTRL
-- Compiling module RCVDLYCNTRL
-- Compiling module RCVPLSTMR
-- Compiling module testfixture

Top level modules:
        testfixture
[mjarabek@scotty verilog]$ vsim -c testfixture           
Reading /net/galactica/home/public/tools/modeltech/6.0d/modeltech/tcl/vsim/pref.tcl 

# 6.0d

# vsim -c testfixture 
# //  ModelSim SE 6.0d Apr 25 2005 SunOS 5.8
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading work.testfixture
# Loading work.APSChip
# ** Warning: (vsim-3009) [TSCALE] - Module 'APSChip' does not have a `timescale directive in effect, but previous modules do.
#         Region: /testfixture/dut
# Loading work.RCVCNTRL
# Loading work.RCVALG
# Loading work.RCVPLSTMR
# Loading work.RCVDLYCNTRL
# ** Fatal: (vsim-3366) APSChip.v(63): Ports cannot be connected by name when a module contains unnamed ports.
#    Time: 0 ps  Iteration: 0  Instance: /testfixture/dut/U23 File: RCVCNTRL.v
# FATAL ERROR while loading design
# Error loading design
Error loading design
[mjarabek@scotty verilog]$
------------

After removing the []'s from RCVCNTL's port list, things compile in Icarus
as well.  When you include a range selection in a module declaration, this
forces the use of `implicit' ports, that is, you are creating a module that
has effectively a single vector as it's input that is the concatenation of
all the parameters.  In your case, you should only be able to instantiate
your module with positional parameters.  I don't think that is what you intended.

Steve, does icarus support implicit declarations like this?  (Not that they
are common, intentionally.)


Mike
Harold D. Skank wrote:

People,

I have created a gEDA schematic comprised of 4 Verilog submodules, each
having its own (hand generated) netlist, along with the attendant IPAD's
and OPAD's.  Each submodule has passed verilog testing using it's own
testfixture file.

I generated a netlist for the schematic using the gEDA command:

gnetlist -g verilog -o APSChip.v APSChip-2.sch

Said netlist (APSChip.v) file is attached below.  From anything I can
see, it seems to have generated just fine, yet when I attempt to perform
a verilog compilation, I get a 2 errors (vlogTST.sav) that I simply
don't understand.  I am attaching the following files:
	RCVALG.v
	RCVCNTRL.v
	RCVDLYCNTRL.v
	RCVPLSTMR.v
	vlogTST.sav
	APSChip.v
	testfixture.v
I would appreciate your reviewing this information and suggesting just
what it is that I'm doing wrong.

	Harold Skank
  

-- 
--------------------------------------------------
                              Mike Jarabek
                                FPGA/ASIC Designer
 http://www.istop.com/~mjarabek
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