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Re: gEDA-user: Verilog netlist problems

Mike Jarabek wrote: 
Hi,

I don't think you want to have things like Gain[7:0] and RcvMsg[11:0] in your module declaration:

module RCVCNTRL(
	StrtAlg,
	Gain[7:0],
	TrnsfrMsg,
	RcvMsg[11:0],
	StrtTmr,
	StrtDly,
	AlgClk,
	CyclDn,
	DlyDn,
	Hit,
	BfrMt,
	TrnsfrDn,
	ClkX64
         );


Those Gain and RcvMsg things are just plain wrong. All the
difficulties would go away if those lines were replaced
with "Gain" and "RcvMsg" and leave the vector sizes to the
input/output declarations inside the module.



--
Steve Williams                "The woods are lovely, dark and deep.
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