Re: gEDA-user: VeriWell now on SourceForge

[Hagen Sankowski <hsank@xxxxxxxxxxxxxxxxxxxx>]

Hello.

Am 29.09.2005 12:41:33 schrieb(en) Evan Lavelle:

> Note that you can't classify the cores unless you actually look at the 
> source code. 

Well, you're right, to show a tendency it was okay. There are some Verilog designs ;-)

> Not relevant to this topic, but there's no peer review process and the 
> cores can be of very low quality. The one Verilog core I've looked at in 
> detail was abysmal.

I agree. But your attribute 'abysmal' belongs to a lot of cores I've seen on opencores.org both in VHDL and in Verilog. I think there are to less fellows to take the peer review. Opencores has to get better quality to get more attention to reach better quality .. You know, the never ending story. Unfortunatly there are less people knowing the business than in the area of software. Open Source Hardware projects doesn't reach the critical mass quite often therefore.

Regards
-- 
Hagen Sankowski              Email: hsank@xxxxxxxxxxxxxxxxxxxx