Re: gEDA-user: VeriWell now on SourceForge

[Evan Lavelle <eml-geda@xxxxxxxxxxx>]

Hagen Sankowski wrote:

> Well, in both tables the same picture we see. There are some more
> designs (54,7%) in VHDL than in Verilog (45,3%) -the same values (in
> %) for booth tables aren't a mistake- !

Note that you can't classify the cores unless you actually look at the 
source code. SystemC cores, for example, are normally classified as 
Verilog. The site also carries this disclaimer:

> Note: language filter doesn't work very well yet because most of
> projects don't have this property set. We are asking developers to
> set it.

Not relevant to this topic, but there's no peer review process and the 
cores can be of very low quality. The one Verilog core I've looked at in 
detail was abysmal.