Hagen Sankowski wrote:
verilog netlist. Well, no problem with synthesis. But why you want a 2nd simulator? Think you've designed your Chip with VHDL, your testbench and all the hard work you've done is in VHDL. Think the fab sends back a routed netlist with the SDF timing model. How you will check it? You can't simulate it 'cause your testbench is in VHDL.
1. Converting a netlist from Verilgo to VHDL can be done by a simple perl script. Remember this is a very basic subset that use a tiny part of the language.
2. Gate level simulations with timing are really rare these days. Instead ,you run a formal verification tool (netlist comparator) against your netlist or against your RTL. The timing is tested by loading it into a static timing analysis tool.