Re: gEDA-user: VeriWell now on SourceForge

[Hagen Sankowski <hsank@xxxxxxxxxxxxxxxxxxxx>]

Hello Samuel.

Am 27.09.2005 08:17:10 schrieb(en) Samuel A. Falvo II:

> What we need isn't a Verilog simulator, what we need is a VHDL
> simulator, and maybe even some means of using both Verilog and VHDL
> together in a single design.  It has always baffled me how Verilog
> simulators seem to be literally everywhere, but if OpenCores is any
> indication, ALL the truely interesting designs are VHDL.

First, please let me ask, what's your profession?
I see a big difference between industrial practise and academic spare time designs. Out of your question I would think you doesn't know the industrial practise, istn't it?

Look at Verilog and you'll see it belongs more to real hardware stuff like gates, wires etc. than VHDL. VHDL doesn't know the concept of primitives, isn't it? Look at VHDL and you'll see it belongs more to behavioral simulation concepts like resolution functions, multi-value wires etc than Verilog. Verilog doesn't support multiple instantiation, generation.. Okay, with quite new IEEE 1394-2001 it should, but Icarus Verilog failed here.

Now look at the fabs, which pay tons of money for the software tools. Cadence, the vendor of the software sales Verilog XL, *the* Verilog simulator. So if you want to make a chip, you have to deliver a verilog netlist. Well, no problem with synthesis. But why you want a 2nd simulator? Think you've designed your Chip with VHDL, your testbench and all the hard work you've done is in VHDL. Think the fab sends back a routed netlist with the SDF timing model. How you will check it? You can't simulate it 'cause your testbench is in VHDL. There's a need now for a Verilog simulator and a verilog testbench. Quite easy, if you've use Verilog from the begining.

At least look at academic designs. There is no need to check the real hardware stuff with an verilog simulator. VHDL looks quite academic with a sophisticated and nearly three-times-slower multi-value signal model. VHDL is used in academic area and for FPGA only ('cause the FPGA tools support both, VHDL and Verilog). In case of quite huge designs, you go to hell if you want simulate all the gates with VHDL in a short time (Example: to simulate how a 32-bit processor boots the first 5 seconds, you take around 2 week simulation time!)

Now you can resume that designs which comes out of the academic / spare time area are mostly VHDL. And all the high volume designs which are working around you are mostly Verilog. Well, now you can think, why VHDL dominates opencores for you? The open source hardware doesn't reached the real design engineers! Most design engineers I know would work with Verilog, but all the academic folks and hobbiest just using VHDL. And so long as designs at opencores.org looks poor (not just because of VHDL) opencores doesn't reach real design engineers.

My conclusion is, to get engineering folks like me with opencores we need a very good verilog simulator (Icarus is one the way, all the things Icarus does, does it well, and back to the topic, Veriwell knows the old verilog standard only) and very good verilog designs.

Regards,
-- 
Hagen Sankowski              Email: hsank@xxxxxxxxxxxxxxxxxxxx