Re: gEDA-user: VeriWell now on SourceForge

[Udi Finkelstein <geda@xxxxxxxx>]

Hagen Sankowski wrote:
> Hello Samuel.
>
> Am 27.09.2005 08:17:10 schrieb(en) Samuel A. Falvo II:
>
>
> > What we need isn't a Verilog simulator, what we need is a VHDL 
> > simulator, and maybe even some means of using both Verilog and VHDL
> >  together in a single design.  It has always baffled me how Verilog
> >  simulators seem to be literally everywhere, but if OpenCores is
> > any indication, ALL the truely interesting designs are VHDL.
>
>
> First, please let me ask, what's your profession? I see a big
> difference between industrial practise and academic spare time
> designs. Out of your question I would think you doesn't know the
> industrial practise, istn't it?
I've been an ASIC designer for the past 7 years as well as an FPGA 
designer before that.

> Look at Verilog and you'll see it belongs more to real hardware stuff
> like gates, wires etc. than VHDL. VHDL doesn't know the concept of
Nobody writes gates these days. Everyone writes stuff like:

assign x = a & b | c;

which can be written equally well in both Verilog and VHDL.

> primitives, isn't it? Look at VHDL and you'll see it belongs more to
> behavioral simulation concepts like resolution functions, multi-value
> wires etc than Verilog. Verilog doesn't support multiple
> instantiation, generation.. Okay, with quite new IEEE 1394-2001 it
> should, but Icarus Verilog failed here.
Verilog doesn't have resolution functions, but it does resolve two 
signals hooked up together. The fact that VHDL is stronger doesn't make 
it less suitable for low level work.
Verilog supports multiple instyantiations. You probably meant array 
instantiations, which was added by Verilog 2001 at the same time the 
generate construct was added. Ofcourse VHDL had those years before.

> Now look at the fabs, which pay tons of money for the software tools.
> Cadence, the vendor of the software sales Verilog XL, *the* Verilog
> simulator. So if you want to make a chip, you have to deliver a
Sorry, but you are out of date. Verilog XL is an interpretted simulator 
that belongs in the Museum. Nobody is using it today. The major 
contenders are Synopsys's VCS and Cadence's NC. Both companies have a 
generic simulation engine and can co-simulate VHDL and Verilog (In 
Synopsys's case, Scirocco-MX for VHDL and VCS-MX for Verilog).

> verilog netlist. Well, no problem with synthesis. But why you want a
> 2nd simulator? Think you've designed your Chip with VHDL, your
> testbench and all the hard work you've done is in VHDL. Think the fab
> sends back a routed netlist with the SDF timing model. How you will
> check it? You can't simulate it 'cause your testbench is in VHDL.
1. Converting a netlist from Verilgo to VHDL can be done by a simple 
perl script. Remember this is a very basic subset that use a tiny part 
of the language.
2. Gate level simulations with timing are really rare these days. 
Instead ,you run a formal verification tool (netlist comparator) against 
your netlist or against your RTL. The timing is tested by loading it 
into a static timing analysis tool.

> There's a need now for a Verilog simulator and a verilog testbench.
> Quite easy, if you've use Verilog from the begining.
>
> At least look at academic designs. There is no need to check the real
> hardware stuff with an verilog simulator. VHDL looks quite academic
> with a sophisticated and nearly three-times-slower multi-value signal
> model. VHDL is used in academic area and for FPGA only ('cause the
This is an implementation issue. I[m quite sure VCS's VHDL front end is 
not 3x slower than its Verilog front-end. Both are compiled.

> My conclusion is, to get engineering folks like me with opencores we
> need a very good verilog simulator (Icarus is one the way, all the
> things Icarus does, does it well, and back to the topic, Veriwell
> knows the old verilog standard only) and very good verilog designs.

My take on this:
At the language level VHDL is stronger than Verilog, even for synthesis 
(VHDL has enums which in theory synthesizers can use for FSM state 
assignment. Verilog lacks this).
Verilog dominates the ASIC world, not because it is better but rather 
because it is simpler, code tends to be less verbose, and its good enough.
SystemVerilog now brings the power and capabilities of VHDL and much 
more, using an extended verilog syntax.

Udi