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Re: gEDA-user: VeriWell now on SourceForge
- To: geda-user@xxxxxxxx
- Subject: Re: gEDA-user: VeriWell now on SourceForge
- From: "Samuel A. Falvo II" <sam.falvo@xxxxxxxxx>
- Date: Mon, 26 Sep 2005 23:17:10 -0700
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On 9/26/05, Evan Lavelle <eml-geda@xxxxxxxxxxx> wrote:
> https://sourceforge.net/projects/veriwell/
> http://www.deepchip.com/items/0447-11.html
What we need isn't a Verilog simulator, what we need is a VHDL
simulator, and maybe even some means of using both Verilog and VHDL
together in a single design. It has always baffled me how Verilog
simulators seem to be literally everywhere, but if OpenCores is any
indication, ALL the truely interesting designs are VHDL.
--
Samuel A. Falvo II